-
1
-
-
4944230409
-
Rapid implementation of a genetic sequence comparator using field-programmable gate arrays
-
C. Sequin, Ed., Santa Cruz, CA, Mar
-
D. P. Lopresti, "Rapid implementation of a genetic sequence comparator using field-programmable gate arrays", in Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, C. Sequin, Ed., Santa Cruz, CA, Mar. 1991, pp. 138-152.
-
(1991)
Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference
, pp. 138-152
-
-
Lopresti, D.P.1
-
2
-
-
0030104367
-
Programmable active memories: Reconfigurable systems come of age
-
PII S1063821096020811
-
J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard, "Programmable active memories: Re-configurable systems come of age", IEEE Transactions on VLSI Systems, vol. 4, no. 1, pp. 56-69,1996. (Pubitemid 126780554)
-
(1996)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.4
, Issue.1
, pp. 56-69
-
-
Vuillemin, J.E.1
Bertin, P.2
Roncin, D.3
Shand, M.4
Touati, H.H.5
Boucard, P.6
-
3
-
-
0031345906
-
Automated target recognition on splash 2
-
J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr
-
M. Rencher and B. Hutchings, "Automated target recognition on Splash 2", in Proceedings of IEEE Workshop on FPGAsfor Custom Computing Machines, J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr. 1997, pp. 192200.
-
(1997)
Proceedings of IEEE Workshop on FPGAsfor Custom Computing Machines
, pp. 192200
-
-
Rencher, M.1
Hutchings, B.2
-
5
-
-
84947941677
-
Implementation of a 2-D fast fourier transform on an FPGA-based custom computing machine
-
W. Moore and W. Luk, Eds., Oxford, UK, Sept Springer-Verlag
-
N. Shirazi, P. M. Athanas, and A. L. Abbott, "Implementation of a 2-D Fast Fourier Transform on an FPGA-based custom computing machine", in Field-Programmable Logic and Applications. 5th International Workshop on Field-Programmable Logic and Applications, W. Moore and W. Luk, Eds., Oxford, UK, Sept. 1995, pp. 282-292, Springer-Verlag.
-
(1995)
Field-Programmable Logic and Applications. 5th International Workshop on Field-Programmable Logic and Applications
, pp. 282-292
-
-
Shirazi, N.1
Athanas, P.M.2
Abbott, A.L.3
-
6
-
-
0031630294
-
FPGA-based sonar processing
-
Monterey, CA, February, ACM/SIGDA, ACM
-
P. Graham and B. Nelson, "FPGA-based Sonar Processing", in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1998, ACM/SIGDA, pp. 201-208, ACM.
-
(1998)
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays
, pp. 201-208
-
-
Graham, P.1
Nelson, B.2
-
7
-
-
11244277821
-
Radiation test results of the virtex FPGA and ZBT SRAM for space based reconfig-urable computing
-
September
-
E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, and A. Salazar, "Radiation test results of the Virtex FPGA and ZBT SRAM for space based reconfig-urable computing", in MAPLD Proceedings, September 1999.
-
(1999)
MAPLD Proceedings
-
-
Fuller, E.1
Caffrey, M.2
Blain, P.3
Carmichael, C.4
Khalsa, N.5
Salazar, A.6
-
8
-
-
1242331699
-
A space-based reconfigurable radio
-
T. P. Plaks and P. M. Athanas, Eds. June, CSREA Press
-
M. Caffrey, "A space-based reconfigurable radio", in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), T. P. Plaks and P. M. Athanas, Eds. June 2002, pp. 49-53, CSREA Press.
-
(2002)
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)
, pp. 49-53
-
-
Caffrey, M.1
-
9
-
-
29144464024
-
Triple module redundancy design techniques for virtex FPGAs
-
Xilinx Corporation, November 1, XAPP197 (vl.0)
-
C. Carmichael, "Triple module redundancy design techniques for Virtex FPGAs", Tech. Rep., Xilinx Corporation, November 1, 2001, XAPP197 (vl.0).
-
(2001)
Tech. Rep.
-
-
Carmichael, C.1
-
10
-
-
0036995793
-
A fault injection analysis of virtex FPGA TMR design methodology
-
F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis, "A fault injection analysis of Virtex FPGA TMR design methodology", in Proceedings of the 6th European Conference on Radiation and its Effects on Components and Systems (RADECS 2001), 2001.
-
(2001)
Proceedings of the 6th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2001)
-
-
Lima, F.1
Carmichael, C.2
Fabula, J.3
Padovani, R.4
Reis, R.5
-
11
-
-
1242309218
-
Radiation testing update, SEU mitigation, and availability analysis of the virtex FPGA for space reconfigurable computing
-
E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula, "Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing", in 3rd Annual Conference on Military and Aerospace Programmable Logic Devices (MAPLD), 2000, p. P30.
-
(2000)
3rd Annual Conference on Military and Aerospace Programmable Logic Devices (MAPLD)
-
-
Fuller, E.1
Caffrey, M.2
Salazar, A.3
Carmichael, C.4
Fabula, J.5
-
12
-
-
0013284645
-
Correcting single-event upsets through virtex partial configuration
-
Xilinx Corporation, June 1, XAPP216 (vl.O)
-
C. Carmichael, M. Caffrey, and A. Salazar, "Correcting single-event upsets through Virtex partial configuration", Tech. Rep., Xilinx Corporation, June 1, 2000, XAPP216 (vl.O).
-
(2000)
Tech. Rep.
-
-
Carmichael, C.1
Caffrey, M.2
Salazar, A.3
-
13
-
-
0042193267
-
Proton testing of SEU mitigation methods for the virtex FPGA
-
C. Carmichael, E. Fuller, J. Fabula, and F. D. Lima, "Proton testing of SEU mitigation methods for the Virtex FPGA", in 4th Annual Conference on Military and Aerospace Programmable Logic Devices (MAPLD), 2001, p. P6.
-
(2001)
4th Annual Conference on Military and Aerospace Programmable Logic Devices (MAPLD)
-
-
Carmichael, C.1
Fuller, E.2
Fabula, J.3
Lima, F.D.4
-
14
-
-
0032312005
-
Current radiation issues for programmable elements and devices
-
December
-
R. Katz, J. J. Wang, R. Koga, K. A. LaBel, J. McCollum, R. Brown, R. A. Reed, B. Cronquist, S. Crain, T. Scott, W. Paolini, and B. Sin, "Current radiation issues for programmable elements and devices", IEEE Transactions on Nuclear Science, vol. 45, no. 6, pp. 2600-2610, December 1998.
-
(1998)
IEEE Transactions on Nuclear Science
, vol.45
, Issue.6
, pp. 2600-2610
-
-
Katz, R.1
Wang, J.J.2
Koga, R.3
Label, K.A.4
McCollum, J.5
Brown, R.6
Reed, R.A.7
Cronquist, B.8
Crain, S.9
Scott, T.10
Paolini, W.11
Sin, B.12
-
15
-
-
0033905005
-
Reconfigurable architectures for System Level Applications of Adaptive Computing
-
B. Schott, S. Crago, R. Parker, L. Carter, C. Chen, J. Czarnaski, M. French, T. Tho, and T. Valenti, "Reconfigurable architectures for system-level applications of adapative computing", VLSI Design, vol. 10, no. 3, pp. 265-279, 2000. (Pubitemid 30594327)
-
(2000)
VLSI Design
, vol.10
, Issue.3
, pp. 265-279
-
-
Schott, B.1
Crago, S.P.2
Parker, R.H.3
Chen, C.H.4
Carter, L.C.5
Czarnaski, J.P.6
French, M.7
Hom, I.8
Tho, T.9
Valenti, T.10
-
17
-
-
70450081781
-
Reliability of programmable Input/Output pins in the presence of configuration upsets
-
September, To Be Published
-
N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, "Reliability of programmable Input/Output pins in the presence of configuration upsets", in Proceedings of the 5th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), September 2002, To Be Published.
-
(2002)
Proceedings of the 5th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD)
-
-
Rollins, N.1
Wirthlin, M.2
Caffrey, M.3
Graham, P.4
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