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Volumn 41, Issue 10, 2006, Pages 2354-2357

Analysis and measurement of signal distortion due to ESD protection circuits

Author keywords

CMOS analog integrated circuits; Electric distortion; Electrostatic discharge

Indexed keywords

CMOS ANALOG INTEGRATED CIRCUITS; ELECTROSTATIC DISCHARGE (ESD); ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS; NONLINEAR CAPACITANCE;

EID: 33749530251     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.881550     Document Type: Conference Paper
Times cited : (14)

References (13)
  • 1
    • 0005416779 scopus 로고    scopus 로고
    • A study of parasitic effects of ESD protection on RF ICs
    • Jan.
    • K. Gong, H. Feng, R. Zhan, and A. Wang, "A study of parasitic effects of ESD protection on RF ICs," IEEE Trans. Microw. Theoiy Tech., vol. 50, no. 1, pp. 393-402, Jan. 2002.
    • (2002) IEEE Trans. Microw. Theoiy Tech. , vol.50 , Issue.1 , pp. 393-402
    • Gong, K.1    Feng, H.2    Zhan, R.3    Wang, A.4
  • 3
    • 0036685489 scopus 로고    scopus 로고
    • Analysis and design of distributed BSD protection circuits for high-speed mixed-signal and RF ICs
    • Aug.
    • C. Ito, K. Banerjee, and R. Dutton, "Analysis and design of distributed BSD protection circuits for high-speed mixed-signal and RF ICs," IEEE Trans. Election Devices, vol. 49, no. 8, pp. 1444-1454, Aug. 2002.
    • (2002) IEEE Trans. Election Devices , vol.49 , Issue.8 , pp. 1444-1454
    • Ito, C.1    Banerjee, K.2    Dutton, R.3
  • 4
    • 0031997302 scopus 로고    scopus 로고
    • Bootstrapped pad protection structures
    • Feb.
    • I. E. Opris, "Bootstrapped pad protection structures," IEEE J. Solid.-State Circuits, vol. 33, no. 2, pp. 301-302, Feb. 1998.
    • (1998) IEEE J. Solid.-state Circuits , vol.33 , Issue.2 , pp. 301-302
    • Opris, I.E.1
  • 5
    • 0034480240 scopus 로고    scopus 로고
    • A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR
    • Dec.
    • H. Pan, M. Segami, M. Choi, C. Ling, and A. A. Abidi, "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1769-1780, Dec. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , Issue.12 , pp. 1769-1780
    • Pan, H.1    Segami, M.2    Choi, M.3    Ling, C.4    Abidi, A.A.5
  • 10
    • 0026838967 scopus 로고
    • Dynamic gate-coupled nMOS for efficient output ESD protection
    • C. Duvvury and C. Diaz, "Dynamic gate-coupled nMOS for efficient output ESD protection," in Proc. Int. Reliability Physics Symp., 1992, pp. 141-150.
    • (1992) Proc. Int. Reliability Physics Symp. , pp. 141-150
    • Duvvury, C.1    Diaz, C.2
  • 12
    • 33749523117 scopus 로고    scopus 로고
    • Frequency domain response of switched-capacitor ADCs
    • R. Reeder, "Frequency domain response of switched-capacitor ADCs," Analog Devices, Application Note AN-742, 2004.
    • (2004) Analog Devices, Application Note , vol.AN-742
    • Reeder, R.1
  • 13
    • 0036923745 scopus 로고    scopus 로고
    • A failsafe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application
    • Dec.
    • J. Lin, C. Duvvury, B. Haroun, I. Oguzman, and A. Somayaji, "A failsafe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application," in IEDM Tech. Dig., Dec. 2002, pp. 349-352.
    • (2002) IEDM Tech. Dig. , pp. 349-352
    • Lin, J.1    Duvvury, C.2    Haroun, B.3    Oguzman, I.4    Somayaji, A.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.