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IEEE Journal of Solid-State Circuits
Volumn 33, Issue 2, 1998, Pages 300-301
Bootstrapped pad protection structure
Author keywords

CMOS integrated circuits; ESD protection
Indexed keywords

CAPACITORS; ELECTRIC DISCHARGES; PROTECTION; SCHEMATIC DIAGRAMS;
EID: 0031997302     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.658635     Document Type: Article
Times cited : (13)
References (2)
  • 1
    • 0026839035 scopus 로고
    • A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI
    • Mar.
    • C.-Y. Wu, M.-D. Kerr, C.-Y. Lee, and J. Ko, "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI," IEEE J. Solid-State Circuits, vol. 27, pp. 274-280, Mar. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 274-280
    • Wu, C.-Y.1    Kerr, M.-D.2    Lee, C.-Y.3    Ko, J.4
  • 2
    • 0030242764 scopus 로고    scopus 로고
    • Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
    • M.-D. Kerr, C.-Y. Wu, T. Cheng, and H.-H. Chang, "Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC," IEEE Trans. VLSI Syst., vol. 4, no. 3, pp. 307-321, 1996.
    • (1996) IEEE Trans. VLSI Syst. , vol.4 , Issue.3 , pp. 307-321
    • Kerr, M.-D.1    Wu, C.-Y.2    Cheng, T.3    Chang, H.-H.4

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.