Reducing instruction fetch cost by packing instructions into register windows

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 19-29

  Hines, Stephen ^a   Tyson, Gary ^a   Whalley, David ^a  

^a Florida State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE SIZE; INSTRUCTION REGISTER FILE (IRF); WINDOWS (OPERATING SYSTEMS);

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE; ENERGY UTILIZATION;

PROGRAM COMPILERS;

EID: 33749403130     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.27     Document Type: Conference Paper

References (24)

1. T. Austin, E. Larson, and D. Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEE Computer, 35:59-67, February 2002.
2. M. E. Benitez and J. W. Davidson. A portable global optimizer and linker. In Proceedings of the SIGPLAN'88 conference on Programming Language Design and Implementation, pages 329-338. ACM Press, 1988.
3. A. Cheng, G. Tyson, and T. Mudge. FITS: Framework-based instruction-set tuning synthesis for embedded application specific processors. In DAC '04: Proceedings of the 41st annual conference on Design Automation, pages 920-923, New York, NY, USA, 2004. ACM Press.
4. K. Cooper and N. McIntosh. Enhanced code compression for embedded rise processors. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 139-149, May 1999.
5. M. Corliss, E. Lewis, and A. Roth. A DISE implementation of dynamic code decompression. In ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, pages 232-243, June 2003.
6. S. K. Debray, W. Evans, R. Muth, and B. DeSutter. Compiler techniques for code compaction. ACM Transactions on Programming Languages and Systems, 22(2):378-415, March 2000.
7. J. Eyre and J. Bier. DSP processors hit the mainstream. IEEE Computer, 31(8):51-59, August 1998.
8. C. W. Fraser, E. W. Myers, and A. L. Wendt. Analyzing and compressing assembly code. In Proceedings of the SIGPLAN '84 Symposium on Compiler Construction, pages 117-121, June 1984.
9. A. Gordon-Ross, S. Cotterell, and F. Vahid. Tiny instruction caches for low power embedded systems. Trans. on Embedded Computing Sys., 2(4):449-481, 2003.
10. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. IEEE 4th Annual Workshop on Workload Characterization, December 2001.
11. S. Hines, J. Green, G. Tyson, and D. Whalley. Improving program efficiency by packing instructions into registers. In Proceedings of the 2005 ACM/IEEE International Symposium on Computer Architecture, pages 260-271. IEEE Computer Society, 2005.
12. N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge. Drowsy instruction caches: Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. In Proceedings of the 35th annual ACM/IEEE International Symposium on Microarchitecture, pages 219-230, Los Alamitos, CA, USA, 2002. IEEE Computer Society Press.
13. J. Kin, M. Gupta, and W. H. Mangione-Smith. The filter cache: An energy efficient memory structure. In Proceedings of the 1997 International Symposium on Microarchitecture, pages 184-193, 1997.
14. K. D. Kissell. MIPS16: High-density MIPS for the embedded market. Technical report, Silicon Graphics MIPS Group, 1997.
15. J. Lau, S. Schoenmackers, T. Sherwood, and B. Calder. Reducing code size with echo instructions. In Proceedings of the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pages 84-94. ACM Press, 2003.
16. L. Lee, B. Moyer, and J. Arends. Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 267-269, 1999.
17. C. Lefurgy, P. Bird, I.-C. Chen, and T. Mudge. Improving code density using compression techniques. In Proceedings of the 1997 International Symposium on Microarchitecture, pages 194-203, December 1997.
18. J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, G. W. Hoeppner, D. Kruckemyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Snyder, R. Stephany, and S. C. Thierauf. A 160-mhz, 32-b, 0.5-W CMOS RISC microprocessor. Digital Tech. J., 9(1):49-62, 1997.
19. S. Segars, K. Clarke, and L. Goudge. Embedded control problems, Thumb, and the ARM7TDMI. IEEE Micro, 15(5):22-30, October 1995.
20. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS-X: Proceedings of the 10th international conference on Architectural Support for Programming Languages and Operating Systems, pages 45-57, New York, NY, USA, 2002. ACM Press.
21. SimpleScalar-ARM Power Modeling Project. http://www.eecs.umich.edu/ ~panalyzer.
22. M. Smith, M. Horowitz, and M. Lam. Efficient superscalar performance through boosting. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, pages 248-259, October 1992.
23. D. Weaver and T. Germond. The S PARC Architecture Manual, 1994.
24. S. J. Wilton and N. P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid State Circuits, 31(5):677-688, May 1996.