A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 189-192

  Cheng, Kuo Hsing ^a   Lo, Yu Lung ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; DIGITAL DEVICES; ELECTRIC DELAY LINES; NETWORKS (CIRCUITS); RANGE FINDERS;

FREQUENCY RANGE SELECTORS; MIXED MODE DELAY LOCKED LOOP (MMDLL); MULTIPHASE OUTPUTS; TIME TO DIGITAL CONVERTER (TDC);

MULTIPATH PROPAGATION;

EID: 33749172822     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541591     Document Type: Conference Paper

References (7)

1. Y. J. Jung et al., "A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines," IEEE J. Solid-State Circuits, vol.36, no.5, pp. 784-791, May. 2001
2. D. J. Foley et al., "CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE J. Solid-State Circuits, vol.36, no.3, pp. 417-423, Mar. 2001.
3. Y. Moon et al., "An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance," IEEE J. Solid-State Circuits, vol.35, no.3, pp. 377-384, Mar. 2000.
4. B.W. Garlepp et al., "A Portable Digital DLL for High-Speed CMOS Interface Circuits," IEEE J. Solid-State Circuits, vol.34, no.5, pp. 632-644, May. 1999.
5. H. H. Chang et al., " A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle," IEEE J. Solid-State Circuits, vol.37, no.8, pp. 1021-1027, Aug. 2002.
6. S. Sidiropoulos et al., "A Semidigital Dual Delay-Locked Loop, " IEEE J. Solid-State Circuits, vol.32, no.11, pp. 1683-1692, Nov. 1997.
7. S. J. Kim et al., "A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM," IEEE J. Solid-State Circuits, vol.37, no.6, pp. 726-734, June. 2002.