A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 44, Issue 3, 2006, Pages 195-217

  Guo, Yuanbin ^a   Cavallaro, Joseph R ^b  

^a NOKIA SIEMENS NETWORKS   (Finland)

^b Rice University   (United States)

Author keywords

Adaptive; CDMA; Interference cancellation; Low power; SoC; VLSI

Indexed keywords

ADAPTIVE SYSTEMS; ALGORITHMS; CODE DIVISION MULTIPLE ACCESS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; INTERFERENCE SUPPRESSION; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

INTERFERENCE CANCELLATION; LOW POWER SOC DESIGN; PARALLEL-RESIDUE-COMPENSATION ARCHITECTURE; SYSTEM-ON-CHIP (SOC) ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 33748704914     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-006-8535-9     Document Type: Article

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