Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2003, Pages 2171-2175

  Guo, Yuanbin ^a   McCain, Dennis ^a   Zhang, Jianzhong ^a   Cavallaro, Joseph R ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; BANDWIDTH; CELLULAR RADIO SYSTEMS; CODE DIVISION MULTIPLE ACCESS; EQUALIZERS; MACHINE DESIGN; MICROPROCESSOR CHIPS; MULTIPLEXING; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; SOFTWARE PROTOTYPING; VLSI CIRCUITS;

HIGH SPEED DOWNLINK PACKET ACCESS (HSDPA); PARALLELISM; SINGLE INPUT MULTIPLE OUTPUT (SIMO); TRADEOFFS;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 4143133431     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. P. Krauss, W. J. Hillery, and M. D. Zoltowski, "MMSE equalization for forward link in 3G CDMA: symbol-level versus chip-level", Proc. of 10th IEEE Workshop on Statistical Signal and Array Processing, pp. 18-22, 2000.
2. K. Hooli, M. Juntti, M. J. Heikkila, P. Komulainen, M. Latvaaho, J. Lilleberg, "Chip-level channel equalization in WCDMA downlink", EURASIP Journal on Applied Signal Processing, Aug. 2002, pp. 757-770.
3. th IEEE Asilomar Conference on Signals, Systems and Computers, 2003.
4. Y. Guo, G. Xu, D. McCain, J. R. Cavallaro, "Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision-C synthesizer", Proc. IEEE Intl. Workshop on Rapid System Prototyping '03, San Diego, CA, pp. 179-185, June2003.