Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2003-January, Issue , 2003, Pages 179-185

  Guo, Yuanbin ^a   Xu, Gang ^a   McCain, D ^a   Cavallaro, J R ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b RICE UNIVERSITY   (United States)

Author keywords

Algorithm design and analysis; Field programmable gate arrays; Graphics; Hardware design languages; Multiaccess communication; Prototypes; Resource management; Synthesizers; Timing; Very large scale integration

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; C++ (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY ALLOCATION; HARDWARE; INTEGRATED CIRCUIT DESIGN; LOCAL AREA NETWORKS; LOGIC SYNTHESIS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; PRODUCT DEVELOPMENT; PRODUCTIVITY; SYSTEM-ON-CHIP; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

ALGORITHM DESIGN AND ANALYSIS; GRAPHICS; HARDWARE DESIGN LANGUAGE; MULTI-ACCESS COMMUNICATIONS; PROTOTYPES; RESOURCE MANAGEMENT; SYNTHESIZERS; TIMING;

DESIGN;

EID: 4143077820     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWRSP.2003.1207046     Document Type: Conference Paper

References (6)

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