Low complexity system-on-chip architectures of parallel-residue- compensation in CDMA systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Guo, Yuanbin ^a   McCain, Dennis ^a   Cavallaro, Joseph R ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; GAUSSIAN NOISE (ELECTRONIC); ITERATIVE METHODS; LOGIC DESIGN; OPTIMIZATION; QUADRATURE PHASE SHIFT KEYING; SCHEDULING; SIGNAL INTERFERENCE; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

MULTIPLE ACCESS INTERFERENCE (MAI); NORMALIZED LEAST-MEAN-SQUARE (NLMS) ALGORITHM; PARALLEL RESIDUE COMPENSATION (PRC) ALGORITHM; SYSTEM-ON-CHIP (SOC);

CODE DIVISION MULTIPLE ACCESS;

EID: 4344688745     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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4. N. Correal, R. M. Buehrer, and B. D. Woemer, "A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation," IEEE JSAC. vol. 17, pp. 613-630, Apr. 1999.
5. G. Xue, J. Weng, T.L.Ngoc and S.Tahar, "Adaptive multistage parallel interference cancellation for CDMA," IEEE JSAC., vol. 17, pp.1815-1827, Oct. 1999.
6. Y. Guo, G. Xu, D. McCain, J. R. Cavallaro, "Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision-C synthesizer", Proc. IEEE Intl. Workshop on Rapid System Prototyping '03, San Diego, CA, pp. 179-185, June 2003.