A probabilistic analysis of pipelined global interconnect under process variations

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 724-729

  Kankani, Navneeth ^a   Agarwal, Vineet ^a   Wang, Janet ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ELECTRIC DELAY LINES; PROBABILISTIC LOGICS; PROBABILITY DENSITY FUNCTION; SAMPLING; UNCERTAIN SYSTEMS;

DELAY METRICS; DUAL PHASE CLOCKING SCHEMES; GLOBAL INTERCONNECTS; PROBABILISTIC ANALYSIS;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33748609352     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118468     Document Type: Conference Paper

References (11)

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