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Volumn 2006, Issue , 2006, Pages 311-316

A new approach to synthesize multiple-output functions using reversible programmable logic array

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; INPUT OUTPUT PROGRAMS; OPTIMIZATION;

EID: 33748565611     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.18     Document Type: Conference Paper
Times cited : (10)

References (20)
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  • 2
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  • 6
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    • Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder
    • Kolkata, India, January
    • H.M.H.Babu and A.R. Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder", 18th International Conference on VLSI Design (Kolkata, India, January 2005) 255-260.
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    • Babu, H.M.H.1    Chowdhury, A.R.2
  • 7
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    • Design of a compact reversible binary coded decimal adder circuit
    • to be published (Accepted for publication)
    • H. M. H. Babu and A. R. Chowdhury, "Design of a Compact Reversible Binary Coded Decimal Adder Circuit", Elsevier Journal of Systems Architecture, to be published in 2005 (Accepted for publication).
    • (2005) Elsevier Journal of Systems Architecture
    • Babu, H.M.H.1    Chowdhury, A.R.2
  • 11
    • 0000328287 scopus 로고
    • Irreversibility and heat generation in the computational process
    • R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research Development, 5 (1961) 183-191.
    • (1961) IBM Journal of Research Development , vol.5 , pp. 183-191
    • Landauer, R.1
  • 12
    • 0036058889 scopus 로고    scopus 로고
    • Transformation rules for designing CNOT-based quantum circuits
    • New Orleans, Louisiana, USA, June 10-14
    • K. Iwama, Y. Kamabayashi, and S. Yamashita, "Transformation rules for designing CNOT-based quantum circuits", In Design Automation Conference, New Orleans, Louisiana, USA, June 10-142002.
    • (2002) Design Automation Conference
    • Iwama, K.1    Kamabayashi, Y.2    Yamashita, S.3
  • 13
    • 17044458279 scopus 로고    scopus 로고
    • Spectral and two-place decomposition techniques in reversible logic
    • August
    • D. M. Miller, "Spectral and two-place decomposition techniques in reversible logic", In Midwest Symposium on Circuits and Systems, August-2002.
    • (2002) Midwest Symposium on Circuits and Systems
    • Miller, D.M.1
  • 17
    • 8344281996 scopus 로고    scopus 로고
    • Reversible cascades with minimal garbage
    • Nov.
    • D. Maslov and G. Dueck, "Reversible Cascades with Minimal Garbage", IEEE Transactions on CAD, Vol. 23, issue 11, Nov. 2004, 1497-1509.
    • (2004) IEEE Transactions on CAD , vol.23 , Issue.11 , pp. 1497-1509
    • Maslov, D.1    Dueck, G.2
  • 18
    • 0018328333 scopus 로고    scopus 로고
    • Multiple-valued logic and the design of programmable logic arrays with decoders
    • England
    • T. Sasao, "Multiple-Valued Logic and The design of Programmable logic arrays with decoders", ISMVL 79, England, 27-37.
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    • Sasao, T.1
  • 19
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    • On the design of multiple-valued PLA's
    • April
    • T. Sasao, "On the design of Multiple-Valued PLA's", IEEE Transactions on Computers, Vol. 38, No. 4, April 1989.
    • (1989) IEEE Transactions on Computers , vol.38 , Issue.4
    • Sasao, T.1
  • 20
    • 0012928469 scopus 로고    scopus 로고
    • Fast heuristic minimization of exclusive sum-of-products
    • August
    • A. Mishchenko and M. Perkowski, "Fast heuristic minimization of exclusive sum-of-products", International Reed-Muller Workshop, August 2001, pp. 242-250.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.