A technique for high bandwidth and deterministic low latency load/store accesses to multiple cache banks

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 313-324

  Neefs, Henk ^a   Vandierendonck, Hans ^a   De Bosschere, Koen ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CACHE MEMORY; CRITICAL PATH ANALYSIS; INTERCONNECTION NETWORKS;

DETERMINISTIC LATENCY; INSTRUCTION LEVEL PARALLELISM; MULTIPLE CACHE BANKS;

PARALLEL PROCESSING SYSTEMS;

EID: 0034581199     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. The alpha 21264 microprocessor
2. Complexity-effective superscalar processors
3. Reducing memory latency via non-blocking and prefetching caches
4. Prefetching using Markov predictors
5. The predictability of data values
6. Correlated load-address predictors
7. Low load latency through sum-addressed memory
8. Performance optimization of pipeline primary caches
9. Streamlining data cache access with fast address calculation
10. Predictive sequential associative cache
11. Speculation techniques for improving load related instruction scheduling
12. Decoupling local variable accesses in a wide-issue superscalar processor