Programming efficiency of stacked-gate flash memories with high-κ dielectrics

NanoSingapore 2006: IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings

Volumn 2006, Issue , 2006, Pages 302-305

  Chen, Y Y ^a,b   Chien, C H ^c   Kin, K T ^a   Lou, J C ^c  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b YUANPEI UNIVERSITY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SIMULATION; ELECTRIC POTENTIAL; FLASH MEMORY; NANOTECHNOLOGY; VELOCITY MEASUREMENT;

HIGH PERMITTIVITY; PROGRAMMING EFFICIENCY; STACKED GATE FLASH MEMORIES; TUNNEL DIELECTRICS (TDS);

DIELECTRIC MATERIALS;

EID: 33748499689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOEL.2006.1609734     Document Type: Conference Paper

References (7)

1. The International Technology Roadmap for Semiconductors, 2003 ed., Semiconductor Industry Association.
2. Y. Y. Chen, C. H. Chien and J. C. Lou, "Characteristics of the inter-poly Al2O3 dielectrics on NH3-nitrided bottom poly-Si for next-generation flash memories," Jpn. J. Appl. Phys., vol. 44, pp. 1704-1710, Apr. 2005.
3. W. -H. Lee, J. T. Clemens, R. C. Keller and L. Manchanda, "A novel high κ inter-poly dielectric (IPD), AUOs for low voltage/high speed flash memories: erasing in msecs at 3.3V," in VLSI Tech. Symp. Dig., 1997, pp. 117-118.
4. K. Yoshikawa, "Research challenges for next decade flash memories," in Int. Electron Devices and Materials Symposia (IEDMS), 2000, pp. 11-18.
5. J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vac. Sci. Technol. B, vol. 18, pp. 1785-1791, 2000.
6. G. D. Wilk, R. M. Wallace and J. M. Anthony, "High-κ gate dielectrics: current status and materials properties considerations," J. Appl. Phys., vol. 89, pp. 5243-5275, May 2001.
7. P. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories, 1999, pp. 42-46.