Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 9, 2006, Pages 2009-2018

  Arnaud, Alfredo ^a,b,c   Fiorelli, Rafaella ^a,b   Galup Montoro, Carlos ^a,d  

^a IEEE   (Uruguay)

^b UNIVERSIDAD DE LA REPÚBLICA   (Uruguay)

^c Catholic University   (Uruguay)

^d FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

Low offset transconductors; MOS analog design; MOS matching; Series parallel transistors

Indexed keywords

LOW OFFSET TRANSCONDUCTORS; MOS ANALOG DESIGN; MOS MATCHING; SERIES-PARALLEL TRANSISTORS;

ACOUSTIC NOISE; ELECTRIC CURRENTS; ELECTRONIC EQUIPMENT; MOS DEVICES; TRANSCONDUCTANCE; TRANSISTORS;

OPERATIONAL AMPLIFIERS;

EID: 33748348647     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.880606     Document Type: Article

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