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Volumn 2799, Issue , 2003, Pages 550-558

Advanced cell modeling techniques based on polynomial expressions

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CURVE FITTING; LOGIC DESIGN; LOGIC SYNTHESIS;

EID: 35248870042     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39762-5_61     Document Type: Article
Times cited : (1)

References (8)
  • 1
    • 35248868611 scopus 로고    scopus 로고
    • Scalable Delay Model for Logic and Physical Synthesis
    • The 16th IFIP World Computer Congress, ICDA, August 2000 Dec.
    • F. Wang and Shir-Shen Chang, "Scalable Delay Model for Logic and Physical Synthesis", The 16th IFIP World Computer Congress, ICDA, August 2000. on VLSI Systems, Vol. 7, No. 4, Dec. 1999.
    • (1999) VLSI Systems , vol.7 , Issue.4
    • Wang, F.1    Chang, S.-S.2
  • 3
    • 35248863745 scopus 로고    scopus 로고
    • Reference Manual, 11, Synopsys
    • Reference Manual, "Library Compiler User Guide," vol. 2, 2000.11, Synopsys.
    • (2000) Library Compiler User Guide , vol.2
  • 7
    • 0036477155 scopus 로고    scopus 로고
    • Least-Square Estimation of Average Power in Digital CMOS Circuits
    • Feb
    • A. Murugavel, et.al., "Least-Square Estimation of Average Power in Digital CMOS Circuits," IEEE Transactions on VLSI System, Vol. 10., No.1, Feb 2002.
    • (2002) IEEE Transactions on VLSI System , vol.10 , Issue.1
    • Murugavel, A.1
  • 8
    • 0035004785 scopus 로고    scopus 로고
    • Average power in digital CMOS circuits using least square estimation
    • A. K. Murugavel et. al., "Average power in digital CMOS circuits using least square estimation," Int. Conf. VLSI Design, pp. 215-220, 2001.
    • (2001) Int. Conf. VLSI Design , pp. 215-220
    • Murugavel, A.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.