Linear gate assignment: A fast statistical mechanics approach

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 12, 1999, Pages 1750-1758

  Linhares, Alexandre ^a   Yanasse, Horacio H ^a   Torreäo, José R A ^b  

^a INSTITUTO NACIONAL DE PESQUISAS ESPACIAIS   (Brazil)

^b FLUMINENSE FEDERAL UNIVERSITY   (Brazil)

Author keywords

Circuit, layout compaction; Optimization; Physical design; Very large scale integration

Indexed keywords

EID: 33747501772     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.811324     Document Type: Article

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