Gate Matrix Layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 4, Issue 3, 1985, Pages 220-231

  Wing, Omar ^a   Huang, Shuo ^a   Wang, Rui ^a  

^a Och Spine at New York Presbyterian Hospitals   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; MATHEMATICAL TECHNIQUES - GRAPH THEORY;

ASSIGNMENT FUNCTIONS; CMOS CIRCUITS; GATE MATRIX LAYOUT; TWO-STAGE APPROACH;

INTEGRATED CIRCUITS;

EID: 0009398678     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1985.1270118     Document Type: Article

References (4)

1. [1] A. D. Lopez and H-F S. Law, “A dense gate matrix layout method for MOS VLSI,” IEEE Trans. Electron Devices, pp. 1671–1675, Aug. 1980.
2. [2] O. Wing, “Automated gate matrix layout,” in Proc. 1982 IEEE Int. Symp. Circuits and Systems, Rome, Italy, pp. 681–685, 1982.
3. [3] T. Ohtsuki, H. Mori, E. S. Kuh, T. Kashiwabara, and T. Fujisawa, “One-dimensional logic gate assignment and interval graphs,” IEEE Trans. Circuits Syst., 675–684, Sept. 1979.
4. [4] T. Ohtsuki, M. Mori, T. Kashiwabara, and T. Fujisawa, “On minimal augmentation to a graph to obtain an interval graph,” J. Computer Syst. Sci., pp. 60–97, Feb. 1981.