One-Dimensional Logic Gate Assignment and Interval Graphs

IEEE Transactions on Circuits and Systems

Volumn 26, Issue 9, 1979, Pages 675-684

  Ohtsuki, Tatsuo ^a   Mori, Hajimu ^a   Kuh, Ernest S ^b   Kashiwabara, Toshinobu ^c   Fujisawa, Toshio ^c  

^a Nippon Electric Company Ltd ^*  (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MATHEMATICAL TECHNIQUES - GRAPH THEORY;

LOGIC DEVICES;

EID: 0018520764     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1979.1084695     Document Type: Article

References (12)

1. A. Weinberger, “Large scale integration of MOS complex logic: A layout method,” IEEE Solid-State Circuits, vol. SC-2, pp. 182–190, Dec. 1967.
2. R. P. Larsen, “Computer-aided preliminary layout design of customized MOS arrays, IEEE Trans Computer, vol. C-20, pp. 512–123, 123, May 1971.
3. E. Wittengeller, “Computer-aided design of large-scale integrated I 2 L logic circuits,” IEEE Solid-State Circuits, vol. SC-12, pp. 199–204, Apr. 1977.
4. S. Goto and E. S. Kuh, “An approach to the two-dimensional placement problem in circuit layout,” IEEE Trans. Circuits Syst., vol. CAS-25, 208–214, Apr. 1978.
5. H. Yoshizawa, H. Kawanishi, and K. Kani, “A heuristic procedure for ordering MOS arrays,” in Proc. 12th Design Automation Conf., 1975, pp. 384–389.
6. T. Asano and K. Tanaka, “A gate placement algorithm for one-dimensional arrays,” J. Information Processing, vol. 1, no. 1, pp. 47–52, 1978.
7. C. Berge, Graphs and Hypergraphs. London: North-Holland, 1970.
8. D. J. Rose, R. E. Tarjan, and G. S. Lueker, “Algorithmic aspects of vertex elimination on graphs,” SIAM J. Comput., vol. 5, no. 2, pp. 266–283, June 1976.
9. D. R. Fulkerson and O. A. Gross, “Incidence matrices and interval graphs,” Pacific J. Math., vol. 15, no. 3, pp. 835–855, 1965.
10. K. S. Booth and G. S. Lueker, “Testing for the consecutive ones property, interval graphs, and graph planarity using PQ-tree algorithms,” J. Comput. System Sci., vol. 13, pp. 335–379, 1976.
11. T. Ohtsuki, H. Mori, T. Kashiwabara, and T. Fujisawa, “On minimal augmentation of a graph to obtain an interval graph,” to be published.
12. A. Hashimoto and J. Stevens, “Wire routing by optimizing channel assignment within large apertures,” Proc. 8th Design Automation Workshop, pp. 155–169, 1971.