Exact and Approximate Solutions for the Gate Matrix Layout Problem

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 1, 1987, Pages 79-84

  Deo, Narsingh ^a   Krishnamoorthy, M S ^b   Langston, Michael A ^b  

^a WASHINGTON STATE UNIVERSITY   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - MATHEMATICAL MODELS; MATHEMATICAL PROGRAMMING, DYNAMIC; MATHEMATICAL TECHNIQUES - MATRIX ALGEBRA;

FAST HEURISTIC ALGORITHMS; GATE MATRIX LAYOUT; ONLINE LAYOUT ALGORITHMS; TRACKS NUMBER MINIMIZATION;

LOGIC DEVICES;

EID: 0023147118     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270248     Document Type: Article

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