OPTIMUM GATE PLACEMENT ALGORITHM FOR MOS ONE-DIMENSIONAL ARRAYS.

Journal of digital systems

Volumn 6, Issue 1, 1982, Pages 1-27

  Asano, Tetsuo ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING - SUBROUTINES;

INTEGRATED CIRCUITS;

EID: 0020102226     PISSN: 01954350     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)