QsNetII: Defining high-performance network design

IEEE Micro

Volumn 25, Issue 4, 2005, Pages 34-47

  Beecroft, Jon ^a   Addison, David ^a   Hewson, David ^a   McLaren, Moray ^a   Roweth, Duncan ^a   Petrini, Fabrizio ^b   Nieplocha, Jarek ^b  

^a Quadrics Ltd   (United Kingdom)

^b PACIFIC NORTHWEST NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER WORKSTATIONS; DATA COMMUNICATION SYSTEMS; INTERFACES (COMPUTER); LOGIC CIRCUITS; MICROCOMPUTERS; MICROPROCESSOR CHIPS; PACKET NETWORKS; RANDOM ACCESS STORAGE; SUPERCOMPUTERS;

CLUSTER COMPUTERS; FUNCTIONAL BLOCK CHARACTERISTICS; HIGH-PERFORMANCE INTERCONNECT; HIGH-PERFORMANCE NETWORK DESIGN; SHORT-MESSAGE PROCESSING UNIT;

NETWORK PROTOCOLS;

EID: 25844504635     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.75     Document Type: Article

References (9)

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