A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1775-1784

  Khan, Aurangzeb K ^a,b   Magoshi, Hidetaka ^a,c   Matsumoto, Tadashi ^d   Fujita, Jun Ichi ^d   Furuhashi, Makoto ^c   Imai, Masatoshi ^d   Kurose, Yoshikazu ^d   Sato, Morio ^d   Sato, Katsuhiko ^d   Yamashita, Yujiro ^d   Kwan, Kinying ^b   Le, Duc Ngoc ^b   Yu, John H ^b   Nguyen, Trung ^b   Yang, Steven ^b   Tsou, Allen ^b   Chow, King ^b   Shen, John ^b   Li, Min ^b   Li, Jun ^b   Zhao, Hong ^b   Yoshida, Kenji ^b   more..

^a IEEE   (United States)

^b Simplex Solutions Inc   (United States)

^c Sony Computer Entertainment Inc   (United States)

^d SONY CORPORATION   (Japan)

Author keywords

Delay estimation; Design methodology; Signal integrity; Very large scale integration design

Indexed keywords

EFFICIENT CURRENT SOURCE MODEL; EMBEDDED DRAM; GRAPHICS RENDERING PROCESSOR; SOFTWARE PACKAGE SPICE;

ALGORITHMS; COMPUTER GRAPHICS; COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; HIGH DEFINITION TELEVISION; INTEGRATED CIRCUIT MANUFACTURE; NUMERICAL ANALYSIS; TRANSISTORS;

MICROPROCESSOR CHIPS;

EID: 6644230074     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962301     Document Type: Article

References (7)

1. A microprocessor with a 128-bit CPU, ten floating point MACs, four floating-point dividers, and an MPEG-2 decoder
2. Delay variability: Sources, impacts and trends
3. Design methodologies for interconnects in GHz + ICs
4. 260-Mb/s mixed-signal single-chip integrated system electronics for magnetic hard-disk drivers
5. Waveform moment methods for improved interconnection analysis
6. Asymptotic waveform evaluation for timing analysis
7. RICE: Rapid interconnect circuit evaluator