Design and development of 130-nanometer ICs for a multi-gigabit switching network system

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 317-320

  Khan, A ^a   Ruparel, K ^b   Joly, C ^b   Ghanta, V ^b   Le, D ^a   Nguyen, T ^a   Yu, J ^a   Yang, S ^a   Ahmed, I ^a   Burnside, N ^a   Chagarlamudi, V ^a   Cheung, M ^a   Chiu, F ^a   Fan, Y ^a   Ge, D ^a   Gill, J ^a   Huang, P ^a   Jayapal, V ^a   Kim, O ^a   Li, M ^a   Mak, H ^a   McKeever, P ^a   Nguyen, S ^a   Rajan, K ^a   Riley, S ^a   Tran, P ^a   Truong, H ^a   Tsou, A ^a   Wang, D ^a   Yang, C ^a   Zhang, J ^a   Zhong, X ^a   more..

^a CADENCE DESIGN SYSTEMS   (United States)

^b CISCO SYSTEMS   (United States)

Author keywords

Clock; Design Methodology; Design Validation; Electrical and Physical Design; Networking IC Design; Power Distribution; Signal Integrity

Indexed keywords

CLOCK DISTRIBUTION; DESIGN METHODOLOGY; DESIGN VALIDATION; ELECTRICAL AND PHYSICAL DESIGN; NETWORKING IC DESIGN; POWER DISTRIBUTION; SIGNAL INTEGRITY;

COMPUTER SIMULATION; ELECTRIC POWER DISTRIBUTION; FLIP CHIP DEVICES; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PRINTED CIRCUIT BOARDS; STATIC RANDOM ACCESS STORAGE; SWITCHING; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 20144387543     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. V. Gerousis., "Design and Modeling Challenges for 90nm and 50nm," In Proceedings of the IEEE CICC, pp. 353-360, September 22, 2003
2. R. Preston et al., "Managing variability on Sub-100nm Designs," In Microprocessor Circuit Design Forum, IEEE ISSCC, February 19, 2004
3. D. Tang et al., "Foundry Technology for 130nm and Beyond SoC," In Proceedings of the IEEE CICC, pp. 343-350, Sep. 22, 2003
4. A. Khan et al., "Design and Development of the First Single-Chip Full-Duplex OC48 Traffic Manager and ATM SAR SoC," IEEE CICC, Sep. '03.
5. D. Desharnais, "Nanometer IC routing requires new approaches," EEDesign.com, December 12, 2003
6. G. Paul et al., "A Scalable 160Gb/s Switch Fabric Processor with 320Gb/s Memory Bandwidth," IEEE ISSCC, February 18, 2004