Implementation of a HiperLAN/2 receiver on the reconfigurable montium architecture

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 2011-2018

  Heysters, Paul M ^a   Rauwerda, Gerard K ^a   Smit, Gerard J M ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COSTS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; MULTIMEDIA SYSTEMS; PROGRAM PROCESSORS; SIGNAL RECEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

DYNAMIC RECONFIGURATION; SYSTEM-ON-CHIP (SOC) ARCHITECTURE; WIRELESS ACCESS;

LOCAL AREA NETWORKS;

EID: 12444277232     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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2. A. Berno, "Time and frequency synchronization algorithms for HIPERLAN/2", MSc. Thesis, University of Padova, Italy, October 2001.
3. V. Baumgarte, F. May, A. Nückel, M.Vorbach & M. Weinhardt, "PACT XPP - A Self-Reconfigurable Data Processing Architecture", Proceedings Engineering of Reconfigurable Systems and Algorithms, pp. 64-70, Las Vegas, USA, June 2001.
4. EASY project, http://easy.intranet.gr.
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8. J. Khun-Jush, P. Schramm, U. Wachsmann & F. Wenger, "Structure and Performance of the HIPERLAN/2 Physical Layer", Proceedings VTC '99-Fall, pp. 2667-2671, Amsterdam, the Netherlands, September 1999.
9. J. Medbo, P. Schramm, "Channel Models for HIPERLAN/2", ETSI/BRAN 3ERI085B, March 1998.
10. SDR Forum, http://www.sdrforum.org.
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12. Software Defined Radio project, http://www.sas.el.utwente.nl/home/SDR.
13. R.E. Ziemer & R.L. Peterson, "Introduction to digital communication", second edition, Prentice Hall, USA, 2001.