Delay fault testing of processor cores in functional mode

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 3, 2005, Pages 610-617

  Singh, Virendra ^a,c   Inoue, Michiko ^a   Saluja, Kewal K ^b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE   (India)

Author keywords

At speed test; Delay fault testing; Processor test; Software based self test

Indexed keywords

COMPUTER SOFTWARE; GRAPH THEORY;

AT-SPEED TEST; DELAY FAULT TESTING; PROCESSOR TEST; SOFTWARE-BASED SELF-TEST;

PROGRAM PROCESSORS;

EID: 24144464315     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.3.610     Document Type: Article

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