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Volumn 5, Issue 4, 2000, Pages 752-773

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

Author keywords

Code size minimization; Custom templates; Design automation; EPIC; Instruction format design; Noop compression; Retargetable assembly; VLIW

Indexed keywords


EID: 33746728297     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/362652.362658     Document Type: Article
Times cited : (17)

References (18)
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    • 5444254612 scopus 로고    scopus 로고
    • Automatic design of VLIW and EPIC instruction formats
    • Hewlett-Packard Laboratories
    • ADITYA, S., RAU, B. R., AND JOHNSON, R. C. 2000. Automatic design of VLIW and EPIC instruction formats. HPL Technical Report HPL-1999-94, Hewlett-Packard Laboratories.
    • (2000) HPL Technical Report HPL-1999-94
    • Aditya, S.1    Rau, B.R.2    Johnson, R.C.3
  • 2
    • 16244407568 scopus 로고    scopus 로고
    • Automatic architectural synthesis of VLIW and EPIC processors
    • (San Jose, California, 1999), IEEE Computer Society
    • ADITYA, S., RAU, B. R., AND KATHAIL, V. 1999. Automatic architectural synthesis of VLIW and EPIC processors. In International Symposium on System Synthesis, ISSS'99 (San Jose, California, 1999), IEEE Computer Society, 107-113.
    • (1999) International Symposium on System Synthesis, ISSS'99 , pp. 107-113
    • Aditya, S.1    Rau, B.R.2    Kathail, V.3
  • 3
    • 6344273745 scopus 로고    scopus 로고
    • Instruction set synthesis using operation pattern detection
    • (Heijen, The Netherlands, 1999)
    • ARNOLD, M. AND CORPORAAL, H. 1999. Instruction set synthesis using operation pattern detection. In Fifth Annual Conference of ASCI (Heijen, The Netherlands, 1999).
    • (1999) Fifth Annual Conference of ASCI
    • Arnold, M.1    Corporaal, H.2
  • 4
    • 0027591918 scopus 로고
    • The cydra 5 mini-supercomputer: Architecture and implementation
    • BECK, G. R., YEN, D. W. L., AND ANDERSON, T. L. 1993. The cydra 5 mini-supercomputer: architecture and implementation. The Journal of Supercomputing 7, 1/2, 143-180.
    • (1993) The Journal of Supercomputing , vol.7 , Issue.1-2 , pp. 143-180
    • Beck, G.R.1    Yen, D.W.L.2    Anderson, T.L.3
  • 7
    • 0031623719 scopus 로고    scopus 로고
    • Instruction selection, resource allocation, and scheduling in the Aviv retargetable code generator
    • HANONO, S. AND DEVADAS, S. 1998. Instruction selection, resource allocation, and scheduling in the Aviv retargetable code generator. In 35th Design Automation Conference (1998), 510-515.
    • (1998) 35th Design Automation Conference (1998) , pp. 510-515
    • Hanono, S.1    Devadas, S.2
  • 14
    • 0023847142 scopus 로고
    • Cydra 5 directed dataflow architecture
    • (San Francisco, 1988)
    • RAU, B. R. 1988. Cydra 5 directed dataflow architecture. In COMPCON '88 (San Francisco, 1988), 106-113.
    • (1988) COMPCON '88 , pp. 106-113
    • Rau, B.R.1
  • 15
    • 0032678801 scopus 로고    scopus 로고
    • Machine-description driven compilers for EPIC and VLIW processors
    • RAU, B. R., KATHAIL, V., AND ADITYA, S. 1999. Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems 4, 2/3, 71-118.
    • (1999) Design Automation for Embedded Systems , vol.4 , Issue.2-3 , pp. 71-118
    • Rau, B.R.1    Kathail, V.2    Aditya, S.3
  • 16
    • 0033892359 scopus 로고    scopus 로고
    • EPIC: Explicitly parallel instruction computing
    • SCHLANSKER, M. S. AND RAU, B. R. 2000. EPIC: Explicitly parallel instruction computing. Computer 33, 2, 37-45.
    • (2000) Computer , vol.33 , Issue.2 , pp. 37-45
    • Schlansker, M.S.1    Rau, B.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.