Automatic design of VLIW and EPIC instruction formats

HP Laboratories Technical Report

Volumn 1999, Issue 94, 2000, Pages

  Aditya, Shail ^a   Rau, B Ramakrishna ^a   Johnson, Richard ^a,b  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b Transmeta Corporation   (United States)

Author keywords

Abstract ISA; Affinity allocation; Bit allocation; Concrete ISA; EPIC processors; HPL PD architecture; Instruction encoding; Instruction format design; Instruction set architecture; Template design; VLIW processors

Indexed keywords

AUTOMATIC DESIGNS; EXPLICITY PARALLEL INSTRUCTUION COMPUTING (EPIC) PROCESSORS; INSTRUCTION FORMATS; VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURES;

ALGORITHMS; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; ROM; WORD PROCESSING;

LOGIC DESIGN;

EID: 5444254612     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

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