Interconnect estimation for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 8, 2006, Pages 1523-1534

  Kannan, Parivallal ^a,b   Bhatia, Dinesh ^a,c  

^a IEEE   (United States)

^b XILINX INC   (United States)

^c The University of Texas at Dallas   (United States)

Author keywords

Congestion; Fast generic routability estimation for placed FPGA circuits (fGREP); Field programmable gate array (FPGA); Interconnect estimation; Routability

Indexed keywords

FAST GENERIC ROUTABILITY ESTIMATION FOR PLACED FPGA CIRCUITS (FGREP); GENERIC ROUTABILITY ESTIMATION; INTERCONNECT ESTIMATION; ROUTABILITY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC POWER SYSTEM INTERCONNECTION; FIELD PROGRAMMABLE GATE ARRAYS; PARAMETER ESTIMATION; ROUTERS;

MOTION PLANNING;

EID: 33746651161     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.857312     Document Type: Article

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