Design and technology of fine-grained sleep transistor circuits in ultra-deep sub-micron CMOS technologies

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 223-228

  Henzler, Stephan ^a   Nirschl, Thomas ^a,b   Berthold, Jörg ^b   Georgakos, Georg ^b   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; LOGIC CIRCUITS;

CHARGE RECYCLING; LOGIC BLOCKS; SLEEP TRANSISTOR CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 25844499210     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502636     Document Type: Conference Paper

References (13)

1. S.I.A.: "ITRS, International Technology Roadmap for Semiconductors", 2002
2. J. W. Tschanz, S.G. Narendra, Y. Ye, B.A. Bloechel, S. Borkar, V. De: "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors", IEEE Journal of Solid State Circuits, Vol. 38, No. 11, 2003
3. R.K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, S. Borkar et al.: "High-performance, Low-power, and Leakage-tolerance Challenges for Sub-70nm Microprocessor Circuits", ESSCIRC 2002
4. H. Kawaguchi, K. Nose, T. Sakurai: "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage With Picoampere Stand-By Current", IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, 2000
5. S. Mutoh, S. Shigematsu, Y. Gotoh, S. Konaka: "Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs", ASP-DAC 1999
6. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada et al.: "l-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, 1995
7. K-S. Min, H. Kawaguchi, T. Sakurai: "Zigzag Super Cut-off CMOS Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era", ISSCC 2003
8. St. Henzler, Th.Nirschl, S. Skiathitis, J. Berthold, J. Fischer, Ph. Teichmann, F. Bauer, G. Georgakos, D. Schmitt-Landsiedel: "Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times", ISSCC 2005
9. J. Kao, A. Chandrakasan, D. Antoniadis: "Transistor Sizing Issues and Tool for MTCMOS Technology", DAC 1997
10. J. Kao, S. Narendra, A. Chandrakasan: "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns", DAC 1998
11. B. H. Calhoun, F.A. Honore, A. Chandrakasan: "Design Methodology for Fine Ggrained Leakage Control in MTCMOS", ISLPED 2003
12. St. Henzler, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel: "Two Level Compact Simulation Methodology For Timing Analysis Of Power-Switched Circuits", PATMOS 2004
13. P. Royannez, H. Main F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, U. Ko: "90nm Low Leakage SoC Design Techniques for Wireless Applications", ISSCC 2005