Predicting cache space contention in utility computing servers

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Solihin, Yan ^a   Guo, Fei ^a   Kim, Seongbeom ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE SHARING; CACHE THRASHING; FINE-GRAIN RESOURCES; UTILITY COMPUTING SERVERS;

COMPUTATION THEORY; ERROR ANALYSIS; MULTIPROCESSING SYSTEMS; PERFORMANCE; SERVERS; UTILITY PROGRAMS;

BUFFER STORAGE;

EID: 33746292710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.354     Document Type: Conference Paper

References (20)

1. A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. A CM Trans. on Computer Systems, 1989.
2. J.-L. Baer and W.-H. Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. In Proc. of the Intl. Symp. on Computer Architecture, 1988.
3. C. Cascaval, L. DeRose, D. A. Padua, and D. Reed. Compile-Time Based Performance Prediction. In Proc. of the 12th Intl. Workshop on Languages and Compilers for Parallel Computing, 1999.
4. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting the impact of inter-thread cache contention on a chip multiprocessor architecture. In Proc. of the 10th Intl. Symp. on High Performance Computer Architecture, 2005.
5. S. Chatterjee, E. Parker, P. Hanlon, and A. Lebeck. Exact analysis of the cache behavior of nested loops. In Proc. of ACM SIGPLAN Conf. on Programming Language Design and Implementation, 2001.
6. B. Fraguela, R. Doallo, and E. Zapata. Automatic analytical modeling for the estimation of cache misses. In Proc. of Intl. Conf. on Parallel Architectures and Compilation Techniques, 1999.
7. S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: a compiler framework for analyzing and tuning memory behavior. A CM Trans. on Programming Languages and Systems, 21(4):703-746, 1999.
8. IBM. IBM Power4 System Architecture White Paper, 2002.
9. J. Renau, et al. SESC. http://sesc.sourceforge.net, 2004.
10. M. Kharbutli, K. Irwin, Y. Solihin, and J. Lee. Using prime numbers for cache indexing to eliminate conflict misses. In Proc. of the Intl. Symp. on High Performance Computer Architecture, 2004.
11. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning on a chip multi-processor architecture. In Proc. of the Intl. Conf. on Parallel Architecture and Compilation Techniques, 2004.
12. J. Lee, Y. Solihin, and J. Torrellas. Automatically Mapping Code on an Intelligent Memory Architecture. In 7th Intl. Symp. on High Performance Computer Architecture, 2001.
13. R. L. Mattson, J. Gecsei, D. Slutz, and I. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2), 1970.
14. Y. Solihin, J. Lee, and J. Torrellas. Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Trans. on Computers: special issue on Advances in High Performance Memory Systems, 2001.
15. Standard Performance Evaluation Corporation. Spec benchmarks, http://www.spec.org, 2000.
16. G. Suh, S. Devadas, and L. Rudolph. Analytical Cache Models with Applications to Cache Partitioning. In Proc. of Intl. Conf. on Supercomputing, 2001.
17. G. E. Suh, S. Devadas, and L. Rudolph. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. In Proc. of Intl. Symp. on High Performance Computer Architecture, 2002.
18. D. Thiebaut, H. Stone, and J. Wolf. Footprints in the cache. ACM Trans. on Computer Systems, 5(4), Nov. 1987.
19. X. Vera and J. Xue. Let's Study Whole-Program Cache Behaviour Analytically. In Proc. of Intl. Symp. on High Performance Computer Architecture, 2002.
20. H. J. Wassermann, O. M. Lubeck, Y. Luo, and F. Bassetti. Performance Evaluation of the SGI Origin2000: A Memory-Centric Characterization of LANL ASCI Applications. In Supercomputing, 1997.