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Volumn 2005, Issue , 2005, Pages 181-190

A comparison of floating point and logarithmic number systems for FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

EXPONENTIATION COMPUTATIONS; LOGARITHMIC NUMBER SYSTEMS;

EID: 33746154954     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.6     Document Type: Conference Paper
Times cited : (48)

References (14)
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  • 2
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    • 2003 The Thrity-Seventh Asilomar Conference on, 9-12 Nov. 2003
    • Detrey, Jérémie and Dinechin, Florent de, "A VHDL Library of LNS Operators", Signals, Systems & Computers, 2003 The Thrity-Seventh Asilomar Conference on , Volume: 2, 9-12 Nov. 2003, Pages:2227 -2231.
    • (2003) Signals, Systems & Computers , vol.2 , pp. 2227-2231
    • Detrey, J.1    De Dinechin, F.2
  • 5
    • 0027226531 scopus 로고
    • An accurate LNS arithmetic unit using interleaved memory function interpolator
    • 1993. Proceedings., 11th Symposium on, 29 June-2 July
    • Lewis, D.M., "An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolator", Computer Arithmetic, 1993. Proceedings., 11th Symposium on, 29 June-2 July 1993, Pages:2-9.
    • (1993) Computer Arithmetic , pp. 2-9
    • Lewis, D.M.1
  • 6
    • 18644369409 scopus 로고    scopus 로고
    • An arithmetic library and its application to the N-body problem
    • FCCM 2004. 12th Annual IEEE Symposium on, 20-23 April 2004
    • Tsoi, K.H., Ho, C.H., Yeung, H.C., Leong, P.H.W., "An arithmetic library and its application to the N-body problem", Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on, 20-23 April 2004 Pages:68-78.
    • (2004) Field-programmable Custom Computing Machines , pp. 68-78
    • Tsoi, K.H.1    Ho, C.H.2    Yeung, H.C.3    Leong, P.H.W.4
  • 7
    • 33746111375 scopus 로고    scopus 로고
    • A parallel look-up logarithmic number system addition/subtraction scheme for FPGA
    • Proceedings. 2003 IEEE International Conference on, 15-17 Dec. 2003
    • Lee, B.R.; Burgess, N., "A parallel look-up logarithmic number system addition/subtraction scheme for FPGA", Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on, 15-17 Dec. 2003 Pages:76-83.
    • (2003) Field-programmable Technology (FPT) , pp. 76-83
    • Lee, B.R.1    Burgess, N.2
  • 9
    • 0032667139 scopus 로고    scopus 로고
    • A 32 bit logarithmic arithmetic unit and its performance compared to floating-point
    • Proceedings. 14th IEEE Symposium on, 14-16 April 1999
    • Coleman, J.N., Chester, E.I.,"A 32 bit logarithmic arithmetic unit and its performance compared to floating-point", Computer Arithmetic, 1999. Proceedings. 14th IEEE Symposium on, 14-16 April 1999 Pages:142-151.
    • (1999) Computer Arithmetic , pp. 142-151
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  • 10
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    • (1994) IEEE Transactions on VLSI Systems , vol.2 , Issue.3 , pp. 365-367
    • Fagin, B.1    Renard, C.2
  • 11
    • 0030396384 scopus 로고    scopus 로고
    • Implementation of IEEE single precision floating point addition and multiplication on FPGAs
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  • 12
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    • Logarithmic number system and floating-point arithemtics on FPGA
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    • (2002) FPL , pp. 627-636
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  • 13
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    • November
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    • (1999) IEE Proc. Comput. Digit. Tech , vol.146 , Issue.6
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.