-
1
-
-
0033131785
-
Efficient algorithms for binary logarithmic conversion and addition
-
May
-
Wan, Y. and Wey, C.L., "Efficient Algorithms for Binary Logarithmic Conversion and Addition," IEE Proceedings, Computers and Digital Techniques, Vol. 146, No.3, pp. 168-176, May 1999.
-
(1999)
IEE Proceedings, Computers and Digital Techniques
, vol.146
, Issue.3
, pp. 168-176
-
-
Wan, Y.1
Wey, C.L.2
-
2
-
-
0013015990
-
-
A.K. Peters, Ltd., Natick, MA
-
nd Edition, A.K. Peters, Ltd., Natick, MA, 2002.
-
(2002)
nd Edition
-
-
Koren, I.1
-
4
-
-
4143080579
-
A VHDL library of LNS operators
-
2003 The Thrity-Seventh Asilomar Conference on, 9-12 Nov. 2003
-
Detrey, Jérémie and Dinechin, Florent de, "A VHDL Library of LNS Operators", Signals, Systems & Computers, 2003 The Thrity-Seventh Asilomar Conference on , Volume: 2, 9-12 Nov. 2003, Pages:2227 -2231.
-
(2003)
Signals, Systems & Computers
, vol.2
, pp. 2227-2231
-
-
Detrey, J.1
De Dinechin, F.2
-
5
-
-
0027226531
-
An accurate LNS arithmetic unit using interleaved memory function interpolator
-
1993. Proceedings., 11th Symposium on, 29 June-2 July
-
Lewis, D.M., "An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolator", Computer Arithmetic, 1993. Proceedings., 11th Symposium on, 29 June-2 July 1993, Pages:2-9.
-
(1993)
Computer Arithmetic
, pp. 2-9
-
-
Lewis, D.M.1
-
6
-
-
18644369409
-
An arithmetic library and its application to the N-body problem
-
FCCM 2004. 12th Annual IEEE Symposium on, 20-23 April 2004
-
Tsoi, K.H., Ho, C.H., Yeung, H.C., Leong, P.H.W., "An arithmetic library and its application to the N-body problem", Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on, 20-23 April 2004 Pages:68-78.
-
(2004)
Field-programmable Custom Computing Machines
, pp. 68-78
-
-
Tsoi, K.H.1
Ho, C.H.2
Yeung, H.C.3
Leong, P.H.W.4
-
7
-
-
33746111375
-
A parallel look-up logarithmic number system addition/subtraction scheme for FPGA
-
Proceedings. 2003 IEEE International Conference on, 15-17 Dec. 2003
-
Lee, B.R.; Burgess, N., "A parallel look-up logarithmic number system addition/subtraction scheme for FPGA", Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on, 15-17 Dec. 2003 Pages:76-83.
-
(2003)
Field-programmable Technology (FPT)
, pp. 76-83
-
-
Lee, B.R.1
Burgess, N.2
-
8
-
-
0034215619
-
Arithmetic on the European logarithmic microprocessor
-
July
-
Coleman, J.N.; Chester, E.I.; Softley, C.I.; Kadlec, J., "Arithmetic on the European logarithmic microprocessor", Computers, IEEE Transactions on,Volume: 49, Issue: 7, July 2000 Pages:702-715.
-
(2000)
Computers, IEEE Transactions on
, vol.49
, Issue.7
, pp. 702-715
-
-
Coleman, J.N.1
Chester, E.I.2
Softley, C.I.3
Kadlec, J.4
-
9
-
-
0032667139
-
A 32 bit logarithmic arithmetic unit and its performance compared to floating-point
-
Proceedings. 14th IEEE Symposium on, 14-16 April 1999
-
Coleman, J.N., Chester, E.I.,"A 32 bit logarithmic arithmetic unit and its performance compared to floating-point", Computer Arithmetic, 1999. Proceedings. 14th IEEE Symposium on, 14-16 April 1999 Pages:142-151.
-
(1999)
Computer Arithmetic
, pp. 142-151
-
-
Coleman, J.N.1
Chester, E.I.2
-
10
-
-
0028501884
-
Field programmable gate arrays and floating point arithmetic
-
Sept.
-
B. Fagin, C. Renard, "Field Programmable Gate Arrays and Floating Point Arithmetic", IEEE Transactions on VLSI Systems, Vol. 2, No. 3, pp. 365-367, Sept. 1994.
-
(1994)
IEEE Transactions on VLSI Systems
, vol.2
, Issue.3
, pp. 365-367
-
-
Fagin, B.1
Renard, C.2
-
11
-
-
0030396384
-
Implementation of IEEE single precision floating point addition and multiplication on FPGAs
-
Louca, Loucas, Cook, Todd A., Johnson, William H., "Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs", FPGA 's for Custom Computing, 1996.
-
(1996)
FPGA's for Custom Computing
-
-
Louca, L.1
Cook, T.A.2
Johnson, W.H.3
-
12
-
-
79955132452
-
Logarithmic number system and floating-point arithemtics on FPGA
-
LNCS 2438
-
Matousek, R., Tichy, M., Pohl, Z., Kadlec, J., Softley, C., Coleman, N., "Logarithmic Number System and Floating-Point Arithemtics on FPGA", FPL, 2002, LNCS 2438, pp. 627-636.
-
(2002)
FPL
, pp. 627-636
-
-
Matousek, R.1
Tichy, M.2
Pohl, Z.3
Kadlec, J.4
Softley, C.5
Coleman, N.6
-
13
-
-
0033337991
-
Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation
-
November
-
Wan, Y., Khalil, M.A., Wey, C.L., "Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation", IEE Proc. Comput. Digit. Tech", Vol. 146, No. 6. November 1999.
-
(1999)
IEE Proc. Comput. Digit. Tech
, vol.146
, Issue.6
-
-
Wan, Y.1
Khalil, M.A.2
Wey, C.L.3
-
14
-
-
2442598143
-
FPGA's vs. CPU's: Trends in peak floating point performance
-
Underwood, Keith, "FPGA's vs. CPU's: Trends in Peak Floating Point Performance," FPGA 04,
-
FPGA 04
-
-
Underwood, K.1
|