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Volumn 2, Issue , 2003, Pages 2227-2231

A VHDL library of LNS operators

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPROXIMATION THEORY; COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSING; ERROR ANALYSIS; MATHEMATICAL OPERATORS;

EID: 4143080579     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (39)

References (9)
  • 1
    • 4143090102 scopus 로고    scopus 로고
    • 21st century slide rules with logarithmic arithmetic: High-speed, low-cost, low-power alternative to fixed point arithmetic
    • February
    • M.G. Arnold. 21st century slide rules with logarithmic arithmetic: High-speed, low-cost, low-power alternative to fixed point arithmetic. In Online Symposium for Electronics Engineers (http://www.osee.net), February 2002.
    • (2002) Online Symposium for Electronics Engineers
    • Arnold, M.G.1
  • 2
    • 0024945885 scopus 로고
    • Redundant logarithmic number systems
    • Ercegovac Avizienis and Swartzlander, editors. Santa Monica, September. IEEE Computer Society Press
    • M.G. Arnold, T.A. Bailey, J.R. Cowles, and J.J. Cupal. Redundant logarithmic number systems. In Ercegovac Avizienis and Swartzlander, editors, Proceedings of the 9th IEEE Symposium on Computer Arithmetic, pages 144-151. Santa Monica, September 1989. IEEE Computer Society Press.
    • (1989) Proceedings of the 9th IEEE Symposium on Computer Arithmetic , pp. 144-151
    • Arnold, M.G.1    Bailey, T.A.2    Cowles, J.R.3    Cupal, J.J.4
  • 3
    • 0034215619 scopus 로고    scopus 로고
    • Arithmetic on the european logarithmic microprocessor
    • July
    • J.N. Coleman and E.I Chester. Arithmetic on the european logarithmic microprocessor. IEEE Transactions on Computers, 49(7): 702-715, July 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , Issue.7 , pp. 702-715
    • Coleman, J.N.1    Chester, E.I.2
  • 4
    • 0034858753 scopus 로고    scopus 로고
    • Some improvements on multipartite table methods
    • Neil Burgess and Luigi Ciminiera, editors, Vail, Colorado, June. Updated version of LIP research report 2000-38
    • F. de Dinechin and A. Tisserand. Some improvements on multipartite table methods. In Neil Burgess and Luigi Ciminiera, editors, 15th IEEE Symposium on Computer Arithmetic, pages 128-135, Vail, Colorado, June 2001. Updated version of LIP research report 2000-38.
    • (2001) 15th IEEE Symposium on Computer Arithmetic , pp. 128-135
    • De Dinechin, F.1    Tisserand, A.2
  • 6
    • 14844338846 scopus 로고    scopus 로고
    • A dual-path logarithmic number system addition/subtraction scheme for FPGA
    • Lisbon, September
    • B. Lee and N. Burgess. A dual-path logarithmic number system addition/subtraction scheme for FPGA. In Field-Programmable Logic and Applications, Lisbon, September 2003.
    • (2003) Field-programmable Logic and Applications
    • Lee, B.1    Burgess, N.2
  • 7
    • 0029485007 scopus 로고
    • 114 MFLOPS logarithmic number system arithmetic unit for DSP applications
    • D.M. Lewis. 114 MFLOPS logarithmic number system arithmetic unit for DSP applications. IEEE Journal of Solid-State Circuits, 30(12):1547-1553, 1995.
    • (1995) IEEE Journal of Solid-state Circuits , vol.30 , Issue.12 , pp. 1547-1553
    • Lewis, D.M.1
  • 8
    • 0024878594 scopus 로고
    • Algorithm design for a 30 bit integrated logarithmic processor
    • Ercegovac Avizienis and Swartzlander. editors, Santa Monica, September. IEEE Computer Society Press
    • D.M. Lewis and L.K. Yu. Algorithm design for a 30 bit integrated logarithmic processor. In Ercegovac Avizienis and Swartzlander. editors, Proceedings of the 9th IEEE Symposium on Computer Arithmetic, pages 192-199, Santa Monica, September 1989. IEEE Computer Society Press.
    • (1989) Proceedings of the 9th IEEE Symposium on Computer Arithmetic , pp. 192-199
    • Lewis, D.M.1    Yu, L.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.