How to obtain accurate resist simulations in very low-k1 era?

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6154 II, Issue , 2006, Pages

  Chiou, Tsann Bim ^a   Park, Chan Ha ^b   Choi, Jae Seung ^b   Min, Young Hong ^a   Hansen, Steve ^c   Tseng, Shih En ^a   Chen, Alek C ^a   Yim, Donggyu ^b  

^a ASML Taiwan Ltd   (Taiwan)

^b Hynix Semiconductor Inc   (South Korea)

^c ASML US Inc   (United States)

Author keywords

CD tolerance; Low k1; Metrology error; Pattern fidelity; Resist model calibration; Simulation accuracy; Weighting factor

Indexed keywords

ALGORITHMS; CALIBRATION; COMPUTER SIMULATION; LIGHT SOURCES; LITHOGRAPHY; PARAMETER ESTIMATION; PROCESS CONTROL; SCANNING ELECTRON MICROSCOPY; SIGNAL PROCESSING;

CD TOLERANCE; LOW-K1; METROLOGY ERROR; PATTERN FIDELITY; RESIST MODEL CALIBRATION; SIMULATION ACCURACY; WEIGHTING FACTOR;

IMAGING SYSTEMS;

EID: 33745805388     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.658990     Document Type: Conference Paper

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