Device performance of transistors with high-κ dielectrics using cross-wafer-scaled interface-layer thickness

IEEE Electron Device Letters

Volumn 27, Issue 7, 2006, Pages 546-548

  O'Sullivan, B J ^a,b   Kaushik, V S ^b,c   Ragnarsson, L A ^b   Onsia, B ^b   Van Hoornick, N ^b   Rohr, E ^b   DeGendt, S ^a,b   Heyns, M ^b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

^c FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Charge; HfO2; Interface layer; Mobility; SiO2; Slant etch; Transistor

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC CHARGE; ETCHING; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

CROSS WAFER; INTERFACE LAYER; SLANT ETCH;

TRANSISTORS;

EID: 33745661890     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.876308     Document Type: Article

References (8)

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