How to characterize the problem of SEU in processors & representative errors observed on flight

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 303-308

  Velazco, R ^a   Ecoffet, R ^b   Faure, F ^a  

^a TIMA LABORATORY   (France)

^b CNES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; ERROR ANALYSIS; INTEGRATED CIRCUITS;

FAULT INJECTION; PROCESSOR-BASED ARCHITECTURE; PROGRAM ERROR RATE; SINGLE EVENT UPSETS (SEU);

PROGRAM PROCESSORS;

EID: 33745484323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.32     Document Type: Conference Paper

References (15)

1. T. Ma, P. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, Wiley Eds., New York, 1989.
2. "Spacecraft system failures and anomalies attributed to the natural space environment", NASA reference publication 1390, August 1996.
3. R. Ecoffet, M. Prieur, M.F. DelCastillo, S. Duzellier, D. Falguère, "Influence of the solar cycle on SPOT-1,-2,-3 upset rates", IEEE Transaction on Nuclear Sciences (TNS), vol 42, no 6, pp. 1983, Dec 1995.
4. R. Harboe-Sorensen, E. Daly, F. Teston, H. Schweitzer, R. Nartallo, P. Perol, F. Vandenbussche, H. Dzitko, J. Cretolle, "Observation and analysis of single event effects on-board the SOHO satellite", Proceedings of Radiation and its Effects on Components and Systems (RADECS 01), Grenoble (France), p. 37, Sept. 2001.
5. C.M. Seidleck, K.A. LaBel, A.K. Moran, M.M. Gates, J.M. Barth, E.G. Stassinopoulos, T.D. Gruner, "Single event effect flight data analysis of multiple NASA spacecraft and experiments; implications to spacecraft electrical design", RADECS 1995 Conference Proceedings, p. 581.
6. F. Bezerra, D. Hardy, R. Velazco and H. Ziade, "TILMICRO, a new SEU latch-up tester for microprocessors initial results on 32-bit floating point DSPs", RADECS Radiation and its effects on Components and Systems, pp. 296-301, 1995.
7. F. Bezerra, D. Benezech, R. Velazco, "Etude de la sensibilité des Transputers aux phénomènes de SEU et latchup". Proc. of RADECS 95, Arcachon, pp. 340-34, 18-23 Septembre 1995.
8. R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, R. Koga, Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits, IEEE Trans Nuclear Science, Vol. 44, no6, p2229 (1994).
9. S. Rezgui, R. Velazco, R. Ecoffet, S. Rodriguez, J.R. Mingo, Estimating Error Rates in Processor-Based Architectures, IEEE TNS, Vol. 48, pp. 1680-1687, Oct. 2000.
10. Velazco R., Rezgui S., Ecoffet R., "Predicting Error Rate for Microprocessor-Based Digital Architectures through C.E.U. (Code Emulating Upsets) Injection", IEEE Transaction on Nuclear Science, Vol. 47, No. 6, pp. 2405-2411, Dec. 2000.
11. th IEEE International Symposium Defect and Fault Tolerance on VLSI systems (DFT 2002), Vancouver (Canada), 6-8 november 2002 pp.108-116.
12. F. Faure, R. Velazco, P. Peronnard, Single Event Upset like Fault Injection: a Comprehensive Framework, accepted for presentation at IEEE Nuclear and Space Radiation Effect Conference (NSREC 2005), Seattle (USA), 12-15 July 2005.
13. S. Rezgui, G. Swift, R. Velazco, F. Faarmanesh, Validation of an SEU technique fo a Complex Processor: Power PC7400, IEEE TNS, Vol. 49, No 6, december 2002, pp. 3156-3162.
14. F. Faure, R. Velazco, M. Violante, M. Rebaudengo, M.S. Reorda, Impact on Data Cache on the Single Event Upset-Induced Error Rate of Microprocessors, IEEE TNS, vol. 50, No. 6, IETNAE, pp.2101-2106, December 2003.
15. F. Faure, P. Peronnard, R. Velazco, R. Ecoffet, "THESIC+: A flexible system for S.E.E. testing ".Proceedings of RADECS'02, Padova (Italy), September 2002.