A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 5, 2000, Pages 713-716

  Hoenigschmid, Heinz ^a,b   Frey, Alexander ^b   DeBrosse, John K ^a   Kirihata, Toshiaki ^a   Mueller, Gerhard ^a   Storaska, Daniel W ^a   Daniel, Gabriel ^a   Frankowsky, Gerd ^a   Guay, Kevin P ^a   Hanson, David R ^a   Hsu, Louis Lu Chen ^a   Ji, Brian ^a   Netis, Dmitry G ^a   Panaroni, Steve ^a   Radens, Carl ^a   Reith, Armin M ^a   Terletzki, Hartmud ^a   Weinfurtner, Oliver ^a   Alsmeier, Johann ^a   Weber, Werner ^b   Wordeman, Matthew R ^a   more..

^a IBM RESEARCH   (United States)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

4 gb; DRAM; Vertical bl

Indexed keywords

EID: 33745011888     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.841498     Document Type: Article

References (6)

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4. H. Cho, et al., A novel pillar DRAM cell for 4-Gbit and beyond, in Symp. on VLSI Tech., 1998, p. 38.
5. H. Nakano, et al., A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAM's, in Symp. on VLSI Circuits, 1996, p: 190.
6. 2 trench cell with a locally-open globally-folded dual bitline for l-Gb/4-Gb DRAM, in Symp. on VLSI Tech., 1998, p. 36.