0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 36-37

  Radens, C J ^a   Gruening, U ^a   Weybright, M E ^a   DeBrosse, J K ^a   Kleinhenz, R L ^a   Hoenigschmid, H ^a   Thomas, A C ^a   Mandelman, J A ^a   Alsmeier, J ^a   Bronner, G B ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CELLULAR ARRAYS;

SHALLOW TRENCH ISOLATION (STI);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0031632530     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)