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Volumn 2, Issue , 2005, Pages 1292-1295
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On chip network: Topology design and evaluation using NS2
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Author keywords
Mesh architecture; NS2; On Chip Network; Topology
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Indexed keywords
ADAPTIVE ALGORITHMS;
ERROR ANALYSIS;
INTELLECTUAL PROPERTY;
INTERCONNECTION NETWORKS;
MICROPROCESSOR CHIPS;
NETWORK PROTOCOLS;
ROUTERS;
SEMICONDUCTOR MATERIALS;
SWITCHING NETWORKS;
TOPOLOGY;
MESH ARCHITECTURE;
MICRON TECHNOLOGIES;
NS2;
ON CHIP NETWORKS;
COMPUTER NETWORKS;
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EID: 33745005763
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (11)
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References (10)
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