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Volumn 2, Issue , 2005, Pages 1292-1295

On chip network: Topology design and evaluation using NS2

Author keywords

Mesh architecture; NS2; On Chip Network; Topology

Indexed keywords

ADAPTIVE ALGORITHMS; ERROR ANALYSIS; INTELLECTUAL PROPERTY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; ROUTERS; SEMICONDUCTOR MATERIALS; SWITCHING NETWORKS; TOPOLOGY;

EID: 33745005763     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (11)

References (10)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan.
    • L. Benini and G. De Micheli, "Networks On Chips: A new SoC paradigm," IEEE computer, Jan. 2002.
    • (2002) IEEE Computer
    • Benini, L.1    De Micheli, G.2
  • 2
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • Apr.
    • M. A. Horowitz et al.,"The future of wires", Proceeding of IEEE, Vol. 89, Issue. 4, pp. 490-504, Apr. 2001.
    • (2001) Proceeding of IEEE , vol.89 , Issue.4 , pp. 490-504
    • Horowitz, M.A.1
  • 5
    • 33744987849 scopus 로고    scopus 로고
    • NS2: www.isi.edu/nsnam/ns/.
    • NS2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.