A Connectivity Based Clustering Algorithm With Application to VLSI Circuit Partitioning

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 5, 2006, Pages 384-388

  Li, Jianhua ^a   Behjat, Laleh ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

Clustering; iterative improvement; partitioning

Indexed keywords

ALGORITHMS; BENCHMARKING; DESIGN FOR TESTABILITY; INTERCONNECTION NETWORKS; ITERATIVE METHODS;

CIRCUIT PARTITIONING; CLUSTERING ALGORITHM;

VLSI CIRCUITS;

EID: 33646896922     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.862174     Document Type: Article

References (17)

1. C. J. Alpert, “The ISPD98 circuit benchmark suite,” in Proc. ACM/IEEE ISPD, 1998, pp. 80–85.
2. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel hy-pergraph partitioning: Application in VLSI domain,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 1, pp. 69–79, Jan. 1999.
3. G. Karypis and V. Kumar, “Multilevel k-way hypergraph partitioning,” in Proc. ACM/IEEE DAC, 1999, pp. 343–348.
4. C. J. Alpert, D. Huang, and A. B. Kahng, “Multilevel circuit partitioning,” IEEE Trans. Comput.-Aided Des. Integr. Circuits, vol. 17, no. 8, pp. 655–667, Aug. 1998.
5. A. E. Caldwell, A. B. Kahng, and I. L. Markov, “Improved algorithms for hypergraph bi-partitioning,” in Proc. Asia South Pacific DAC, 2000, pp. 661–666.
6. C. J. Alpert and A. B. Kahng, “Recent directions in netlist partitioning: A survey,” VLSI J. Integr., vol. 19, pp. 1–81, 1995.
7. S. Dutt and W. Deng, “Probability-based approaches to vlsi circuit partitioning,” IEEE Trans. Comput.-Aided Des. Integr. Circuits, vol. 19, pp. 534–549, 2000.
8. C. M. Fiduccia and R. M. Mattheyses, “A linear time heuristic for improving network partitions,” in Proc. ACM/IEEE DAC, 1982, pp. 175–181.
9. L. W. Hagen, D. J. Huang, and A. B. Kahng, “On implementation choices for iterative improvement partitioning methods,” in Proc. Eur. DAC, 1995, pp. 144–149.
10. J. Cong and S. Lim, “Edge separability-based circuit clustering with application to multilevel circuit partitioning,” IEEE Trans. Comput.-Aided Des. Integr. Circuits, vol. 23, no. 3, pp. 346–357, 2004.
11. J. Cong, M. Romesis, and M. Xie, “Optimality, scalability, and stability study of partitioning and placement algorithms,” in Proc. ACM/IEEE ISPD, 2003, pp. 88–94.
12. Y. Saab, “An effective multilevel algorithm for bisecting graphs and hy-pergraphs,” IEEE Trans. Comput., vol. 53, no. 6, pp. 641–652, Jun. 2004.
13. S. Wichlund and E. Aas, “On multilevel circuit partitioning,” in Proc. IEEE ICCAD, 1998, pp. 505–511.
14. S. Hauck and G. Borriello, “An evaluation of bipartitioning techniques,” IEEE Trans. Comput.-AidedDes. Integr. Circuits Syst., vol. 16, no. 8, pp. 849–866, 1997.
15. B. Hu and M. Marek-Sadowska, “Fine granularity clustering for large scale placement problems,” in Proc. ACM/IEEE ISPD, 2003, pp. 61-64.
16. J. Cong and M. Smith, “A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design,” in Proc. ACM/IEEE DAC, 1993, pp. 755–760.
17. C. J. Alpert. (2004) ISPD98—Circuit Benchmark Errata. [Online]. Available: http://vlsicad.cs.ucla.edu/cheese/errata.html