Probability-based approaches to VLSI circuit partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 5, 2000, Pages 534-549

  Dutt, Shantanu ^a   Deng, Wenyong ^b  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; PROBABILITY;

CLUSTERING EFFECTS; ITERATIVE IMPROVEMENT TECHNIQUES; LOOKAHEAD GAIN CALCULATION METHOD; MIN CUT PARTITIONING; PROBABILISTIC PARTITIONER; VLSI CIRCUIT PARTITIONING;

VLSI CIRCUITS;

EID: 0033716817     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.845078     Document Type: Article

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