Analysis and modeling of layout scaling in silicon integrated stacked transformers

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 5, 2006, Pages 2203-2210

  Blondi, Tonio ^a,b,d   Scuderi, Angelo ^a,c,d   Ragonese, Egidio ^a,c,d   Palmisano, Giuseppe ^c  

^a IEEE   (Italy)

^b STMICROELECTRONICS   (Italy)

^c UNIVERSITY OF CATANIA   (Italy)

^d Radio Frequency Advanced Design Center (RF ADC)   (Italy)

Author keywords

Integrated transformers; Layout scaling; Lumped modeling; On wafer measurements; RF integrated circuits (ICs)

Indexed keywords

INTEGRATED TRANSFORMERS; LAYOUT SCALING; LUMPED MODELING; ON-WAFER MEASUREMENTS; RF INTEGRATED CIRCUITS; WIDEBAND LUMPED MODELS;

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; INDUCTANCE; MAGNETIC COUPLINGS; MONOLITHIC INTEGRATED CIRCUITS; RESONANCE; SILICON;

ELECTRIC TRANSFORMERS;

EID: 33646734035     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2006.872788     Document Type: Article

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