A scalable and multiplier-less fully-pipelined architecture for VLSI implemetation of discrete Hartley transform [implemetation read implementation]

SCS 2003 - International Symposium on Signals, Circuits and Systems, Proceedings

Volumn 2, Issue , 2003, Pages 393-396

  Meher, P K ^a   Srikanthan, T ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE;

DISCRETE HARTLEY TRANSFORMS; EXISTING STRUCTURE; FULLY PIPELINED ARCHITECTURE; HARDWARE IMPLEMENTATIONS; HIGH THROUGHPUT; MULTIPLIER-LESS; SPEED PERFORMANCE; VLSI IMPLEMENTATION;

VLSI CIRCUITS;

EID: 33646572013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SCS.2003.1227072     Document Type: Conference Paper

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