-
1
-
-
10444258917
-
-
Irving S, Liu Y. Free drop test simulation for portable IC package by implicit transient dynamics FEM. In: Proc 54th electronic components and technology conference, Las Vegas, NV, 2004. p. 1062-6.
-
-
-
-
2
-
-
10444248113
-
-
Lall P, Panchagade D, Liu Y, Johnson W, Suhling J. Models for reliability prediction of fine-pitch BGAs and CSPs in shock and drop-impact. In: Proc 54th electronic components and technology conference, Las Vegas, NV, 2004. p. 1296-303.
-
-
-
-
3
-
-
33646484021
-
-
Yeh C-L, Lai Y-S. Effect of solder joint shapes on free drop reliability of chip-scale packages. In: Proc IMAPS Taiwan technical symposium 2004, Kaohsiung, Taiwan, 2004.
-
-
-
-
4
-
-
0036290751
-
-
Kujala A, Reinikainen T, Ren W. Transition to Pb-free manufacturing using land grid array packaging technology. In: Proc 52nd electronic components and technology conference, San Diego, CA, 2002. p. 359-64.
-
-
-
-
5
-
-
32844469702
-
-
Wong EH, Lim KM, Lee N, Seah S, Hoe C, Wang J. Drop impact test-mechanics and physics of failure. In: Proc 4th electronics packaging technology conference, Singapore, 2002. p. 327-33.
-
-
-
-
6
-
-
84954039444
-
-
Tee TY, Ng HS, Zhong Z. Design for enhanced solder joint reliability of integrated passives device under board level drop test and thermal cycling test. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 210-6.
-
-
-
-
7
-
-
10444285597
-
-
Ren W, Wang J. Shell-based simplified electronic package model development and its application for reliability analysis. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 217-22.
-
-
-
-
8
-
-
36249022907
-
-
Xu L, Wang J, Reinikainen T, Han ZX, Wang BP. Numerical studies of the mechanical response of solder joint to drop/impact load. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 228-32.
-
-
-
-
9
-
-
84954043857
-
-
Luan J-E, Tee TY, Pek E, Lim CT, Zhong Z. Modal analysis and dynamic responses of board level drop test. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 233-43.
-
-
-
-
10
-
-
84954048210
-
-
Tan LB, Seah SKW, Wong EH, Zhang X, Tan VBC, Lim CT. Board level solder joint failures by static and dynamic loads. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 244-51.
-
-
-
-
11
-
-
33847300053
-
-
Geng P, Beltman WM, Chen PH, Daskalakis G, Shia D, Williams MH. Modal analysis for BGA shock test board and fixture design. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 252-5.
-
-
-
-
12
-
-
84954072376
-
-
Wang YQ, Low KH, Che FX, Pang JHL, Yeo SP. Modeling and simulation of printed circuit board drop test. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 263-8.
-
-
-
-
13
-
-
84954065778
-
-
Pang JHL, Low KH, Xiong BS, Che FX. Design for reliability (DFR) methodology for electronic packaging assemblies. In: Proc 5th electronics packaging technology conference, Singapore, 2003. p. 470-8.
-
-
-
-
14
-
-
2942740958
-
Impact life prediction modeling of TFBGA packages under board level drop test
-
Tee T.Y., Ng H.S., Lim C.T., Pek E., and Zhong Z. Impact life prediction modeling of TFBGA packages under board level drop test. Microelectron Reliab 44 7 (2004) 1131-1142
-
(2004)
Microelectron Reliab
, vol.44
, Issue.7
, pp. 1131-1142
-
-
Tee, T.Y.1
Ng, H.S.2
Lim, C.T.3
Pek, E.4
Zhong, Z.5
-
15
-
-
10444247304
-
-
Tee TY, Luan J-E, Pek E, Lim CT, Zhong Z. Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact. In: Proc 54th electronic components and technology conference, Las Vegas, NV, 2004. p. 1088-94.
-
-
-
-
16
-
-
10444238042
-
-
Amagai M, Toyoda Y, Ohnishi T, Akita S. High drop test reliability: lead-free solders. In: Proc 54th electronic components and technology conference, Las Vegas, NV, 2004. p. 1304-9.
-
-
-
-
17
-
-
33646484299
-
-
Lai Y-S, Yang P-F, Yeh C-L, Tsai C-I. Board-level drop performance of lead-free chip-scale packages with different soldermask openings and solder compositions. In: Proc 6th international conference on electronics materials and packaging, Penang, Malaysia, 2004. p. 56-60.
-
-
-
-
18
-
-
28444457466
-
-
Chang D, Bai F, Wang YP, Hsiao CS. The study of OSP as reliable surface finish of BGA substrate. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 149-53.
-
-
-
-
19
-
-
28444492703
-
-
Chong DYR, Ng K, Tan JYN, Low PTH, Pang JHL, Che FX. Drop test reliability assessment of leaded and lead-free solder joints for IC packages. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 210-7.
-
-
-
-
20
-
-
28444453001
-
-
Luan J-E, Tee TY. Novel board level drop test simulation using implicit transient analysis with input-G method. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 671-7.
-
-
-
-
21
-
-
28444473143
-
-
Jie G, Lim CT, Tay AAO. Modeling of solder joint failure due to PCB bending during drop impact. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 678-83.
-
-
-
-
22
-
-
28444490052
-
-
Wang YY, Wang F, Chai TC. Finite element modeling of CSP package subjected to board level drop test. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 684-8.
-
-
-
-
23
-
-
28444441992
-
-
Yeh C-L, Lai Y-S. Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications. In: Proc 6th electronics packaging technology conference, Singapore, 2004. p. 695-700.
-
-
-
-
24
-
-
30844434820
-
-
Yeh C-L, Lai Y-S. Support excitation scheme for transient analysis of JEDEC board-level drop test. Microelectron Reliab, in press, doi:10.1016/j.microrel.2004.12.021.
-
-
-
-
25
-
-
33745712153
-
-
Heaslip GM, Punch JM, Rodgers BA, Ryan C, Reid M. A stress-life methodology for ball grid array lead-free and tin-lead solder interconnects under impact conditions. In: Proc 6th international conference on thermal, mechanical and multiphysics simulation and experiments in micro-electronics and micro-systems (EuroSimE 2005), Berlin, Germany, 2005. p. 277-84.
-
-
-
-
26
-
-
33646478809
-
-
Chang W, Jiang D-S, Selvaduray G. CSP drop test performance comparison for different solder ball materials. In: Proc IPC/JEDEC 8th international conference on lead free electronic components and assemblies, San Jose, CA, 2005.
-
-
-
-
27
-
-
33646488743
-
-
Yeh C-L, Lai Y-S. Theoretical framework for response spectra analysis for drop tests with half-sine impact acceleration pulses. In: Proc 3rd conference on microelectronics technology and applications, Kaohsiung, Taiwan, 2005.
-
-
-
-
28
-
-
24644473712
-
-
Syed A, Kim SM, Lin W, Khim JY, Song ES, Shin JH, et al. A methodology for drop performance prediction and application for design optimization of chip scale packages. In: Proc 55th electronic components and technology conference, Lake Buena Vista, FL, 2005. p. 472-9.
-
-
-
-
29
-
-
24644454370
-
-
Groothuis S, Chen C, Kovacevic R. Parametric investigation of dynamic behavior of FBGA solder joints in board-level drop simulation. In: Proc 55th electronic components and technology conference, Lake Buena Vista, FL, 2005. p. 499-503.
-
-
-
-
30
-
-
24644514491
-
-
Tee TY, Luan J-E, Ng HS. Development and application of innovational drop impact modeling techniques. In: Proc 55th electronic components and technology conference, Lake Buena Vista, FL, 2005. p. 504-12.
-
-
-
-
31
-
-
24644446520
-
-
Luan J-E, Tee TY. Effect of impact pulse parameters on consistency of board level drop test and dynamic responses. In: Proc 55th electronic components and technology conference, Lake Buena Vista, FL, 2005. p. 665-73.
-
-
-
-
32
-
-
33646470104
-
-
Yeh C-L, Tsai T-Y, Lai Y-S. Response spectra analysis for JEDEC board-level drop test. In: Proc IMAPS Taiwan 2005 international technical symposium, Taipei, Taiwan, 2005. p. 71-9.
-
-
-
-
33
-
-
30844472660
-
-
Lai Y-S, Yang P-F, Yeh C-L. Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition. Microelectron Reliab, in press, doi:10.1016/j.microrel.2005.07.005.
-
-
-
-
34
-
-
33646490205
-
-
JEDEC Solid State Technology Association. JESD22-B110: subassembly mechanical shock, 2001.
-
-
-
-
35
-
-
33646487240
-
-
JEDEC Solid State Technology Association. JESD22-B111: board level drop test method of component for handheld electronics products, 2003.
-
-
-
-
36
-
-
6344253125
-
Time-independent elastic-plastic behaviour of solder materials
-
Wiese S., and Rzepka S. Time-independent elastic-plastic behaviour of solder materials. Microelectron Reliab 44 12 (2004) 1893-1900
-
(2004)
Microelectron Reliab
, vol.44
, Issue.12
, pp. 1893-1900
-
-
Wiese, S.1
Rzepka, S.2
-
37
-
-
0038480111
-
Effect of simulation methodology on solder joint crack growth correlation and fatigue life prediction
-
Darveaux R. Effect of simulation methodology on solder joint crack growth correlation and fatigue life prediction. J Electron Packaging ASME 124 3 (2002) 147-154
-
(2002)
J Electron Packaging ASME
, vol.124
, Issue.3
, pp. 147-154
-
-
Darveaux, R.1
-
38
-
-
33646477916
-
-
Wang TH, Lai Y-S. Prediction of board-level cyclic bending reliability of wafer-level chip-scale packages. In: Proc IMAPS Taiwan 2005 international technical symposium, Taipei, Taiwan, 2005. p. 29-33.
-
-
-
|