Three hardware architectures for the binary modular exponentiation: Sequential, parallel, and systolic

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 3, 2006, Pages 627-633

  Nedjah, Nadia ^a   de Macedo Mourelle, Luiza ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

Cryptography; Exponentiation; Modular; Multiplication

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; SYSTOLIC ARRAYS;

CORNERSTONE COMPUTATION; SYSTOLIC ARRAY-BASED ARCHITECTURE; THREE HARDWARE ARCHITECTURES;

CRYPTOGRAPHY;

EID: 33645889684     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.858767     Document Type: Article

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