Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

Volumn , Issue , 2002, Pages 226-233

  Nedjah, N ^a   Mourelle, Luiza De MacEdo ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

Computer architecture; Concurrent computing; Field programmable gate arrays; Hardware; Iterative algorithms; Prototypes; Public key; Public key cryptography; Systems engineering and theory; Time factors

Indexed keywords

ALGORITHMS; BINS; COMPUTATION THEORY; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; ITERATIVE METHODS; MICROPROCESSOR CHIPS; PUBLIC KEY CRYPTOGRAPHY; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

CONCURRENT COMPUTING; ITERATIVE ALGORITHM; PROTOTYPES; PUBLIC KEYS; SYSTEMS ENGINEERING AND THEORIES; TIME FACTORS;

COMPUTER HARDWARE;

EID: 84895323118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2002.1115373     Document Type: Conference Paper

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