Two hardware implementations for the Montgomery modular multiplication: Sequential versus parallel

Proceedings - 15th Symposium on Integrated Circuits and Systems Design, SBCCI 2002

Volumn , Issue , 2002, Pages 3-8

  Nedjah, N ^a   De Macedo Mourelle, L ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUITS; ITERATIVE METHODS; PUBLIC KEY CRYPTOGRAPHY; SYSTEMS ANALYSIS; SYSTOLIC ARRAYS;

ARRAY BASED ARCHITECTURE; FPGA PROTOTYPES; HARDWARE IMPLEMENTATIONS; MODULAR MULTIPLICATION; MONTGOMERY ALGORITHM; MONTGOMERY MODULAR MULTIPLICATION; RSA CRYPTOSYSTEMS;

RECONFIGURABLE HARDWARE;

EID: 84965121689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2002.1137629     Document Type: Conference Paper

References (15)

1. R. Rivest, A. Shamir and L. Adleman, A method for obtaining digital signature and public-key cryptosystems, Communications of the ACM, 21:120-126, 1978.
2. E. F. Brickell, A survey of hardware implementation of RSA, In G. Brassard, ed., Advances in Crypltology, Proceedings of CRYPTO'98, Lecture Notes in Computer Science 435:368-370, Springer-Verlag, 1989.
3. C. D. Walter, Systolic modular multiplication, IEEE Transactions on Computers, 42(3):376-378, 1993.
4. S. E. Eldridge and C. D. Walter, Hardware implementation of Montgomery's Modular Multiplication Algorithm, IEEE Transactions on Computers, 42(6):619-624, 1993.
5. J. Rabaey, Digital integrated circuits: A design perspective, Prentice-Hall, 1995.
6. th. Symposium of Computer Architecture and High Performance Computing, IFIP, Brasilia, Brazil, September 2001.
7. N. Nedjah, L. M. Mourelle, Simulation Model for Hardware implementation of modular multiplication, Proceedings of WSES/IEEE International. Conference on Simulation, Knights Island, Malta, September 2001.
8. N. Nedjah, L. M. Mourelle, Reduced Hardware Architecture for the Montgomery Modular Multiplication, Proceedings of the third WSEAS/IEEE Symposium Mathematical Methods and Computational Techniques in Electrical Engineering, Athens, Greece, December 2001.
9. P.L. Montgomery, Modular Multiplication without trial division, Mathematics of Computation 44, pp. 519-521, 1985.
10. Z. Navabi, VHDL - Analysis and Modeling of Digital Systems, McGraw Hill, Second Edition, 1998.
11. MyCad, Inc. and Seodu Logic, Inc., MyVHDL Station V 4.0 Tutorial, http://www.mycad.com or http://www.mycad.co.kr.
12. A. Booth, A signed binary multiplication technique, Quarterly Journal of Mechanics and Applied Mathematics, pp. 236-240, 1951.
13. G. W. Bewick, Fast multiplication algorithms and implementation, Ph. D. Thesis, Department of Electrical Engineering, Stanford University, United States of America, 1994.
14. C. D. Walter, A verification of Brickell's fast modular multiplication algorithm, International Journal of Computer Mathematics, 33:153:169, 1990.
15. Xilinx, Inc. Foundation Series Software, http://www.xilinx.com.