Suppression of high-resistance phases of Ni silicide by Se passivation of Si(100)

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 719-723

  Shanmugam, Janadass ^a   Zhu, Jinggang ^a   Xu, Yuqing ^b   Kirk, Wiley P ^a   Tao, Meng ^a  

^a University of Texas at Arlington   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Integrated circuit metallization; MOSFETs; Nickel compounds; Semiconductor metal interfaces; Surface treatment

Indexed keywords

INTEGRATED CIRCUITS; METALLIZING; MONOLAYERS; MOSFET DEVICES; NICKEL COMPOUNDS; PASSIVATION; SURFACE TREATMENT; SURFACES; TRANSMISSION ELECTRON MICROSCOPY; X RAY DIFFRACTION ANALYSIS; X RAY PHOTOELECTRON SPECTROSCOPY;

HIGH RESISTANCE PHASES; INTEGRATED CIRCUIT METALLIZATION; SEMICONDUCTOR METAL INTERFACES;

SEMICONDUCTING SILICON;

EID: 33645746762     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870569     Document Type: Article

References (15)

1. SEMATECH, International Technology Roadmap for Semiconductors, 2005 Edition, Austin, TX, 2004.
2. T. T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, and H. Iwai, "Self-aligned nickel-monosilicide technology for high-speed deep submicrometer logic CMOS ULSI," IEEE Trans. Electron Devices, vol. 42, no. 5, pp. 915-922, May 1995.
3. C. Lavoie, F. M. d'Heurle, C. Detavernier, and C. Cabral, Jr., "Towards implementation of a nickel silicide process for CMOS technologies," Microelectron. Eng., vol. 70, no. 2-4, pp. 144-157, Nov. 2003.
4. 2 thin films," J. Electrochem. Soc., vol. 141, no. 5, pp. 1347-1350, 1994.
5. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," in IEDM Tech. Dig., San Francisco, CA, 2000, pp. 45-48.
6. 2 on silicon," Jpn. J. Appl. Phys. Suppl., vol. 2, pt. 1, pp. 669-672, 1974.
7. H. Iwai, T. Ohguro, and S. Ohmi, "NiSi silicide technology for scaled CMOS," Microelectron. Eng., vol. 60, no. 1-2, pp. 157-169, Jan. 2002.
8. Y. Tsuchiya, A. Tobioka, O. Nakatsuka, H. Ikeda, A. Sakai, S. Zaima, and Y. Yasuda, "Electrical properties and solid-phase reactions in Ni/ Si(100) contacts," Jpn. J. Appl. Phys. 1, Regul. Rap. Short Notes, vol. 41, no. 4B, pp. 2450-2454, Apr. 2002.
9. S. J. Eglash, N. Newman, S. Pan, D. Mo, K. Shenai, W. E. Spicer, F. A. Ponce, and D. M. Collins, "Engineered Schottky barrier diodes for the modification and control of Schottky barrier heights," J. Appl. Phys., vol. 61, no. 11, pp. 5159-5169, Jun. 1987.
10. M. Tao, J. Shanmugam, M. Coviello, and W. P. Kirk, "Suppression of silicon (001) surface reactivity using a valence-mending technique," Solid State Commun., vol. 132, no. 2, pp. 89-92, 2004.
11. E. Kaxiras, "Semiconductor-surface restoration by valence-mending adsorbatEs: Application to Si(100):S and Si(100):Se," Phys. Rev. B, Condens. Matter, vol. 43, no. 8, pp. 6824-6827, Mar. 1991.
12. M. C. Poon, F. Deng, M. Chan, W. Y. Chan, and S. S. Lau, "Resistivity and thermal stability of nickel monosilicide," Appl. Surf. Sci., vol. 157, no. 1-2, pp. 29-34, 2000.
13. M. Tao and W. P. Kirk, "Monatomic layer passivation of semiconductor surfaces," U.S. Patent No. 6784 114, Aug. 31, 2004.
14. H. Foll, P. S. Ho, and K. N. Tu, "Transmission electron microscopy of the formation of nickel silicides," Philos. Mag. A, Phys. Condens. Matter Defects Mech. Prop., vol. 45, no. 1, pp. 31-47, 1981.
15. S. Ramamurthy, B. Ramachandran, J. S. Byun, T. Dixit, A. Hunter, and R. Ramanujam, "Nickel silicides in semiconductor processing: Thermal budget considerations," Mater. Sci. Eng. B, vol. 114-115, pp. 46-50, Dec. 2004.