A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Lee, Sang Bo ^a   Jang, Seong Jin ^a   Kwak, Jin Seok ^a   Hwang, Sang Jun ^a   Cho, Seong Ho ^a   Park, Min Sang ^a   Lee, Ho Kyoung ^a   Lee, Woo Jin ^a   Lee, Yu Rim ^a   Cho, Young Cheol ^a   Heo, Hyoung Jo ^a   Shin, Won Hwa ^a   Lee, Jong Soo ^a   Park, Yun Sik ^a   Kim, Seok Jung ^a   Jang, Young Uk ^a   Hwang, Seok Won ^a   Jun, Young Hyun ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DATA BUS; DATA LINES; PARALLEL REGISTERS; WRITE CURRENTS;

CONTROL SYSTEMS; DATA TRANSFER; ELECTRIC CURRENTS; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442667590     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. H.Y. Song, et al. "A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die-Termination," ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2003.
2. K. Itoh, et al. "Limitations and Challenges for Multigigabit DRAM Chip Design," IEEE J. Solid-State Circuits, pp. 624-634, Feb. 1997.