A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Kim, Kyu Hyoun ^a   Lee, Jung Bae ^a   Lee, Woo Jin ^a   Jeong, Byung Hoon ^a   Cho, Geun Hee ^a   Lee, Jong Soo ^a   Byun, Gyung Su ^a   Kim, Changhyun ^a   Jun, Young Hyun ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK DIAGRAMS; CHARGE INJECTIONS; DUTY ERRORS; PULL DOWN CURRENTS;

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ITERATIVE METHODS; JITTER; PHASE LOCKED LOOPS; TRANSFER FUNCTIONS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442670172     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. B. Razavi, "Design of Analog CMOS Integrated Circuits," McGraw-Hill Book Company, pp. 564-566, 2001.
2. J.-B. Lee et al., "Digitally Controlled DLL and I/O Circuits for 500Mb/s/pin x16 DDR SDRAM," ISSCC Dig. Tech. Papers, pp. 68-69, Feb. 2001.
3. K-H. Kim et al., "Built-in Duty Cycle Corrector Using Coded Phase Blending Scheme for DDR/DDR2 Synchronous DRAM Application," Dig. Symp. VLSI Circuits, pp. 287-288, Jun. 2003.