A 512Mbit, 1.6Gbps/pin DDR3 SDRAM prototype with CIO minimization and self-calibration techniques

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 370-373

  Park, Churoo ^a   Chung, Hoeju ^a   Lee, Yun Sang ^a   Kim, Jae Kwan ^a   Lee, Jae Jun ^a   Chae, Moo Sung ^a   Jung, Dae Hee ^a   Choi, Sung Ho ^a   Seo, Seung Young ^a   Park, Taek Seon ^a   Shin, Jun Ho ^a   Cho, Jin Hyung ^a   Lee, Seunghoon ^a   Kim, Kyu Hyoun ^a   Lee, Jung Bae ^a   Kim, Changhyun ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; LOGIC DESIGN; SOFTWARE PROTOTYPING; SYNCHRONOUS MACHINERY;

ESD PROTECTION; HYBRID LATENCY CONTROL; PER-BANK-REFRESH; SYNCHRONOUS DRAM PROTOTYPE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33645683157     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469407     Document Type: Conference Paper

References (3)

1. K. Kim, et al., "A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application," in ISSCC Dig. Tech. Papers, 2004, pp. 212-523.
2. S. Lee, et al., "A 1.6 Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control," in ISSCC Dig. Tech. Papers, 2004, pp. 210-213.
3. H. Song, et al., "A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination," in ISSCC Dig. Tech. Papers, 2003, pp. 314-496.